target-arm: aarch64: add preliminary support for MSR/MRS

this is very very limited: we only support
setting and getting NZCV (C4.3.10),
getting CTR_EL0 (D8.2.21) with a hardcoded value,
getting DCZID_EL0 (D8.2.23) with a hardcoded value,
getting and setting TPIDR_EL0 (D8.2.87).

Eventually this could be rewritten on top of arm_cp_regs API
with some refactoring necessary (main issue: ARM_CP_64BIT)

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure, put common code
          between MSR/MRS in a separate function, add NZCV,
          add support for writing to TPIDR_EL0,
          fixed high bit of CTR_EL0]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 35/60, 36/60
target-arm: aarch64: add support for conditional branches

This patch adds emulation for the conditional branch (b.cond) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure,
          reused arm infrastructure for checking the flags]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 34/60