Internals: Prep to allow future move of wrapping. No functional change.
Internals: Refactor V3Inline to simplify if(m_cellp) out. No functional change.
Internals: If registered, dump symtable on any error
Internals: (see last) also dump on first non-fatal
Internals: When broken link fatal, say which rule violated
Internals: V3Inline support for future hard-no-inline. No functional change.
Internals: Misc cleanups from interface branch. No functional change.
Support interfaces and modports, bug102.
Duplicate clock gate optimization on by default, use -Od to disable
Version bump.
Version bump
Merge branch 'master' into verilog-short-circuit