i965: Add a new infrastructure for generating Broadwell shader assembly.

This replaces the brw_eu_emit.c layer for Broadwell.  It will be
used by both the vector and scalar shader backends.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Create a new vec4 backend for Broadwell.

This replaces the old vec4_generator backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Create a new fragment shader backend for Broadwell.

This replaces the old fs_generator backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vs: Always store pull constant offsets in GRFs on Gen8.

We need to SEND from a GRF, and we can only obtain those prior to
register allocation.

This allows us to do pull constant loads without the MRF hack.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vs: Don't copy propagate into SEND-from-GRF messages.

SEND can't deal with swizzles, source modifiers, and so on.  This should
avoid problems with VS pull constant loads on Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Duplicate gen7_atoms to gen8_atoms.

It's going to diverge significantly.  Starting out with a copy allows
future patches to change atoms one by one.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Use the Sandybridge VUE format on Broadwell as well.

It hasn't changed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Bump generation assertions on workaround flushes.

These workaround flushes may not be necessary on Gen8.  Investigation is
needed.  Tentatively, let's do them out of caution.

v2: [chadv]
  - Comment that flush may not be needed.
  - Make assertion conditions symmetrical.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Introduce an OUT_RELOC64 macro.

Broadwell uses 48-bit addresses.  The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.

Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits.  So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update SF, SBE, and RASTER state for Broadwell.

The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add the new 3DSTATE_PS_BLEND state packet.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Rework 3DSTATE_VS for Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update STATE_BASE_ADDRESS for Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update invariant state for Broadwell.

The only difference is that STATE_SIP takes a 48-bit address, so we need
to output two zeroes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Rework vertex uploads for Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update 3DSTATE_CLIP for Broadwell.

Broadwell doesn't have GEN6_CLIP_Z_TEST, and doesn't make you specify
the polygon winding information (it pulls that information from other
packets).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Double the push constant space multipliers on Broadwell too.

Broadwell has 2Kb push constant size increments like Haswell GT3.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update the code that disables unused shader stages for Broadwell.

This may or may not be necessary, but it shouldn't hurt.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>