fix issue #1 - throws an exception when extracting an out-of-range bit
fix issue #4 - added warnings for out-of-bounds reads and writes to mem_t instances
added unit test for issue #6
Merge pull request #61 from smirolo/master

fix a couple long standing issues
tutorial: some minor clearifications
set unique password and send an e-mail after instance is deployed
Replace build.sbt by project/build.scala on Henry's advise.
It permits to compile chisel as a sub-project/git submodule of the reference-chip.
Merge pull request #63 from smirolo/master

making it easier to build reference-chip when chisel is imported as a git submodule
compiles with clang++
Merge pull request #64 from smirolo/master

compiles with clang++
have C++ genHarness emit code for managing multiple clock domains
Merge branch 'master' of github.com:ucb-bar/chisel
Merge pull request #62 from schoeberl/master

tutorial: some minor clearifications (questions marked in comments need to be addressed)
Merge branch 'master' of github.com:ucb-bar/chisel
only emit clocks in testharness for clocks w/o src
fix bugs in doc and smooth out presentation
merge
bump version number to 2.0.4 - add examples on homepage
enable putting an associated password for each account
Merge pull request #65 from smirolo/master

getting ready for bootcamp