clk: zynq: pll: Fix wait for PLL lock

The condition for waiting for the PLL lock when enabling the PLL was
inversed, waiting for a non-locked PLL.
Invert the condition when waiting for the PLL lock, so we actually wait
for a locked PLL.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xemacps: Disable clocks only once

When the driver is removed clocks may be disabled due to runtime PM. If
this happens, remove() must not disable the clocks again. Therefore,
check the runtime PM status in remove() and take the appropriate action.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
net: xemacps: Free net_device after it is used last

The net_device structure is freed to early. Free it after its last user
is done.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
spi: xilinx-qps: Use readl/writel for read/write register

Use readl/writel api's instead of raw read/write registers.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: xilinx-qps: Modified comments for LQSPI register masks

Modified comments for LQSPI Config register TWO_MEM and
SEP_BUS bit masks.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: xilinx-qps: Added macros for bank instructions and lqspi

Opcode definitions for Bank instructions of Spansion and Micron.
Opcode definition for Flag status register read and added these
opcodes to Instruction format table.

Macro for linear qspi config register upper page bit mask.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: xilinx-qps: Remove switch logic in xqspips_copy_read_data

Instead of switch cases, handle the copy of data from rxd
to buffer using memcpy with check on endianess.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: xilinx-qps: Modify the tx logic to use txd1/2/3

Tx logic is modified to utilize TxD1/2/3 registers and few
other constraints.
Transmit length is split into multiples of 4 bytes and the
remainder is transmitted using TxD1/2/3. Also, a transmit on
TxD1/2/3 needs a check for Tx empty before using TXD0 and
vice versa. Towards this requirement, tx_fill_fifo is updated
to fill only if tx length is greater than 4 bytes. For any length
the remainder bytes is first pushed to TxD1/2/3 and enables
interrupts to wait for tx empty interrupt and transfer the remaining
in interrupt routine.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Fix spansion bank reg comment and fix above 80 char lines

Changed the comment for spansion bank read opcode and
break the lines larger than 80 chars.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Increase wait duration during read

Increased the value of MAX_READY_WAIT_JIFFIES from 40 to 480
based on the inputs from Micron considering large size flash
memories.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Modified Micron 256Mb flash info structure entry

Modified entry for micron flash memory 256Mb. Member name is
suffix with 'a13'.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Add Micron flash entries for greater than 256Mb size

Added entries for micron flash memories for sizes 256Mb, 512Mb and
1Gb including voltage variants.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Created E_FSR flag for Micron n25q family flash devices

Created new flag E_FSR in flash_info structure to support
flag status register present in n25q Micron flash family.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Add member jedec_id to m25p structure

Added jedec_id variable to hold id of flash memory.
Updated in probe call with the detected flash ID.

This needs discussion on mainline and will be re-visited
later.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Create read_spi_reg and add read for flag status reg

Created read_spi_reg to perform atomic register read operation.
Added read_fsr and modified read_sr to call read_spi_reg.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Add check on flag status register for Micron flash devices

In wait_till_ready, after poll on status register, if check_fsr is set
poll on flag status register to check no program/erase operation
is in execution. check_fsr is set only if E_FSR flag is added to
flash entry in flash_info structure.

This needs discussion on mainline and will be re-visited
later.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Add support to program bank or extended address register

Added opcode to program extended address register. Added function
write_ear to program bank or extended address register. Added curbank
member to m25p structure.

This needs discussion on mainline and will be re-visited
later.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Modify m25p_addr2cmd logic

Instead of directly copying the addr to cmd buffer, use a
for loop based on the addr width.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: xilinx: Force 3 byte addressing for zynq qspi for large flash size

Hack the addr width to 3 in case of large size flash connected to
zynq qspi controller and force this only if the connected spi controller
is zynq ps qspi.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: m25p80: Add erase/read/write support for large flash sizes

Added support for large size flash memories greater than 16MB using
3 byte addressing and bank selection.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>