Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212.

They are failing in assertions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197669 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the COFF files with Z7 debug info from the repo

Rationale: going to land D2425 shortly.
I'll re-land these COFF files along with D2425 to simplify the SVN history

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197673 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the llvm-readobj COFF dumper to dump debug line tables from object files

Reviewed at http://llvm-reviews.chandlerc.com/D2425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197674 91177308-0d34-0410-b5e6-96231b3b80d8
Add an explicit insert point argument to SplitBlockAndInsertIfThen.

Currently SplitBlockAndInsertIfThen requires that branch condition is an
Instruction itself, which is very inconvenient, because it is sometimes an
Operator, or even a Constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197677 91177308-0d34-0410-b5e6-96231b3b80d8
[dfsan] Simplify code after r197677.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197679 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for PointerLikeRegClass to FixedLenDecoderEmitter

This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter
should recognize PointerLikeRegClass operands as register types, and generate
register-like decoding calls instead of treating them like immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197680 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Introduce LIT in add_lit_target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197682 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-config: Show build root instead of parent path in build tree with --obj-root for CMake multiconfig.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197683 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-config: Don't show build tree with --obj-root for installed llvm-config. Show $(prefix) instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197684 91177308-0d34-0410-b5e6-96231b3b80d8
Support for microMIPS TLS relocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197685 91177308-0d34-0410-b5e6-96231b3b80d8
Add a triple so that this passes on OS X.

I am surprised I am the first one to notice this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197689 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for positionally-encoded operands to FixedLenDecoderEmitter

Unfortunately, the PowerPC instruction definitions make heavy use of the
positional operand encoding heuristic to map operands onto bitfield variables
in the instruction definitions. Changing this to use name-based mapping is not
trivial, however, because additional infrastructure needs to be designed to
handle mapping of complex operands (with multiple suboperands) onto multiple
bitfield variables.

In the mean time, this adds support for positionally encoded operands to
FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC
backend. To prevent an accidental reliance on this feature, and to prevent an
undesirable interaction with existing disassemblers, a backend must opt-in to
this support by setting the new decodePositionallyEncodedOperands
instruction-set bit to true.

When enabled, this iterates the variables that contribute to the instruction
encoding, just as the encoder does, and emulates the procedure the encoder uses
to map "numbered" operands to variables. The bit range for each variable is
also determined as the encoder determines them. This map is then consulted
during the decoder-generator's loop over operands to decode, allowing the
decoder to understand both position-based and name-based operand-to-variable
mappings.

As noted in the comment on the decodePositionallyEncodedOperands definition,
this support should be removed once it is no longer needed. There should be no
change to existing disassemblers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197691 91177308-0d34-0410-b5e6-96231b3b80d8
Support for microMIPS LL and SC instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197692 91177308-0d34-0410-b5e6-96231b3b80d8
Add a disassembler to the PowerPC backend

The tests for the disassembler were adapted from the encoder tests, and for the
most part, the output from the disassembler matches that encoder-test inputs.
There are some places where more-informative mnemonics could be produced
(notably for the branch instructions), and those cases are noted in the tests
with FIXMEs.

Future work includes:

 - Generating more-informative mnemonics when possible (this may also be done
   in the printer).

 - Remove the dependence on positional "numbered" operand-to-variable mapping
   (for both encoding and decoding).

 - Internally using 64-bit instruction variants in 64-bit mode (if this turns
   out to matter).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
Long doubles are required to be aligned to 128 bits and svr4 32 bits.

Clang was already getting this right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197694 91177308-0d34-0410-b5e6-96231b3b80d8
Support for microMIPS control instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197696 91177308-0d34-0410-b5e6-96231b3b80d8
Small simplification, p0 is the same as p.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197699 91177308-0d34-0410-b5e6-96231b3b80d8
Move testcase to the appropriate X86 subdirectory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197701 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r197682, "[CMake] Introduce LIT in add_lit_target."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197703 91177308-0d34-0410-b5e6-96231b3b80d8
Improved fix for PR17827 (instcombine of shift/and/compare).

This change fixes the case of arithmetic shift right - do not attempt to fold that case.
This change also relaxes the conditions when attempting to fold the logical shift right and shift left cases.

No additional IR-level test cases included at this time. See http://llvm.org/bugs/show_bug.cgi?id=17827 for proofs that these are correct transformations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197705 91177308-0d34-0410-b5e6-96231b3b80d8