Fix issue where VGA output would be corrupted when the CPU was writing heavily to memory.
- The VGA controller makes a new memory request when the previous one has been satisfied.  This means it normally ping pongs with the CPU. This would be fine, but there isn't enough memory bandwidth for both masters to saturate the bus. A related issue was that the VGA controller used 8 beat bursts and the CPU used 16 beat bursts, which meant the former only got 1/3 of the total bus capacity.  Lengthened the VGA burst length to 32 so the breakdown is reversed.
- The SDRAM controller now prefers reads to writes. However, if when it tried to initiate a new burst the read FIFO was full and a write was pending, it would service that.  That is normally a good thing: it is improving utilization of SDRAM.  However, that makes it more fair, which is not what we want in this situation (since reads are from VGA in this case).  Altered it so it will always try to complete read transactions before servicing writes.