[FIX] Fix architecture selection of SPI slave entity

This fix prevents errors in Qsys designs using POWERLINK IP-Core together
with SPI bridge.
- PDI SPI is fixed to synchronous clock architecture
- SPI bridge is fixed to asynchronous clock architecture

Change-Id: Ib9887c3cf81230a51cc797fd5b968410e61b5581
Reviewed-on: http://brateggevoat1/gerrit/1434
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Revise release scripts

- Remove release directory cleanup
- Add parameter to set release target directory

Change-Id: Ibc9c579159a4d5aff2c98daac05a62ef052503f1
Reviewed-on: http://brateggevoat1/gerrit/1437
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Enable modelsim synthesis check

This enables the synthesis checker included in modelsim.

Change-Id: I2610c0d6280cc80bbbc0de50c783d098e6d480e9
Reviewed-on: http://brateggevoat1/gerrit/1439
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add global constants for true and false

Change-Id: Iec26a57326109c4c3e279fb943d355aaa2e8ca7f
Reviewed-on: http://brateggevoat1/gerrit/1440
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>