Merge pull request #2 from skristiansson/for-openrisc

cores: update mor1kx.core files
wb_bfm: Added wb_bfm_transactor
Remove deprecated core wb_utils

Users of wb_utils should migrate to wb_intercon instead.
This will break the (probably already broken) generic system
wb_sdram_ctrl: Added simulation support
initial WIP for sockit system
sockit/rom: do endless loop instead of jump to 0x100
sockit: add internal SRAM
clkgen: remove sdram clock signals
clkgen: remove pll files and instantiate pll directly in clkgen.v
orpsoc_top: remove sdram clock and reset
orpsoc_top: remove intgen address decoding
remove olofk bug comment
pinmap: make section comments "block comments"
orpsoc_top: increase internal SRAM to 64KB
orpsoc_top: module declaration signals lineup
remove uart pad signals

There are no pins on the board to hook up an uart,
so we'll just connect them inside the fpga.
format fix
sockit: add qsys generated hps (hard processor system)