R600: Change the RAT instruction assembly names so they match the docs

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188515 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add IsExport bit to TableGen instruction definitions

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Enable folding of inline literals into REQ_SEQUENCE instructions

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188517 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for v4i32 stores on Cayman

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188518 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for i16 and i8 global stores

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for global vector stores with elements less than 32-bits

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188520 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for global vector loads with element types less than 32-bits

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188521 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions

The SIInsertWaits pass was overwriting the first operand (gds bit) of
DS_WRITE_B32 with the second operand (value to write).  This meant that
any time the value to write was stored in an odd number VGPR, the gds
bit would be set causing the instruction to write to GDS instead of LDS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188522 91177308-0d34-0410-b5e6-96231b3b80d8