OMAP4460: add Reverse Body-Bias support to ABB LDO

On 4460 all OPPs have pre-determined states for VDD_MPU's ABB LDO,
except for OPP_TURBO.  OPP_TURBO may require bypass, FBB or RBB
depending on a combination of characterisation data blown into eFuse
register CONTROL_STD_FUSE_OPP_DPLL_1.

Bits 18 & 19 of that register signify DPLL_MPU trim (see
arch/arm/mach-omap2/omap4-trim-quirks.c).  OPP_TURBO might put MPU's ABB
LDO into bypass or FBB based on this value.

Bit 20 siginifies if RBB should be enabled.  If set it will always
override the values from bits 18 & 19.

The table below captures the valid combinations:

Bit 18 | Bit 19 | Bit 20 | ABB type
0        0        0        bypass
0        1        0        bypass  (invalid combo)
1        0        0        FBB     (2.4GHz DPLL_MPU)
1        1        0        FBB     (3GHz DPLL_MPU)
0        0        1        RBB
0        1        1        RBB     (invalid combo)
1        0        1        RBB     (2.4GHz DPLL_MPU)
1        1        1        RBB     (3GHz DPLL_MPU)

This patch introduces ABB type detection into the ABB init code and
makes a few changes to the ABB programming code to allow for RBB (which
was previously unsupported).

This patch also changes OPP_TURBO's default abb_type to FAST_OPP (FBB)
by default.  This tiny optimization benefits production silicon by
removing one PRCM register write from the ABB initialization code for
the common case where the DPLL_MPU trim values are blown in and the
silicon is weak or nominal (uses FBB at OPP_TURBO).

Change-Id: I73973ddbb77dd89a7e2809bc56d935767f20a5d8
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4460: OPP: Move ABB update for MPU OPP turbo to OPP init code

Initially ABB type update was implemented in ABB init code.
This leads to a voltage values duplication.
This patch moves ABB type detection into the OPP init code.

Change-Id: I6140dff1be0f2b9e667160da957c8e1dbabf3e8f
[taras@ti.com: remove previous implementation]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
[nm@ti.com: movement of code to central opp update]
Signed-off-by: Nishanth Menon <nm@ti.com>
[mturquette@ti.com: original author]
Signed-off-by: Mike Turquette <mturquette@ti.com>

Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/ldo.c
	arch/arm/mach-omap2/opp4xxx_data.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
panel-s6e8aa0: fix slightly inaccurate pixel clock

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: fix pclk divisor limits

According to TRM, minimal pixel clock divisor value can be 1.
Fix corresponding checks, as high resolution panels use undivided
pixel clock frequency.

Also certain scaler unit constraint must be met: in case DISPC_CLK
and pixel clock frequencies are equal, set IPC to work on rising edge.

Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: more precise scale limits checking

Use division with rounding-up when checking if maximum downscale ratio
was reached. This allows to avoid SYNC_LOST errors in case when small
amount of extra pixels or lines (usually 1-3) not taken into account

Change-Id: Id8f88c64671146a64738cfd820378bb7a28c1455
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
Add assembler versions of AES and SHA1 for ARM platforms.  This has provided
up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: DSS: Implement workaround for Errata ID:i733.

Description of Errata i733:
Due to wrong timings, all register accesses transitioning through the L4
interconnect toward DSS are not reliable.

Workaround:
DSS register access should be addressed through the L3 interconnect.

This change fixes errata by using L3 for access to DSS in dss_hwmod
instead of L4.

Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0

Change-Id: Ie087b861ee653a3beeacba74c3afe7b1a0490ed4
Co-author: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP: EMIF: fix LP_MODE_PWR_DN value definition

OMAP: EMIF: fix LP_MODE_PWR_DN value definition

According to TRM the EMIF Power-down mode is identified
by value 0x4 (EMIF_PWR_MGMT_CTRL.REG_LP_MODE)

Change-Id: I4d9b9534dea27ab4619af5b6d78de8ab14f0fead
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: fix overconsumption on OFF mode

The wrong value of CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 2 (SW_WKUP)
has been stored in SAR during omap4_sar_save() execution and
causes power over consumption on OFF mode due to C2C operation.
It happens because the L3INIT CD need to be enabled during
omap4_sar_save() execution for proper USBHOST module context storing.

Problematic use case:
1) OMAP goes to sleep,
2) modem wakeup the C2C, the EMIF but the MPU is still sleeping
(as expected)
3) Modem release all his constraints, C2C is turned to OFF.
4) but OMAP never reach again OFF while we don't wakeup the CPU
(by a keypress for example), sys_clk is already ON and voltages
are not equal to 0. (OPP 50 for CORE_3 and retention voltages
for both VCORE1 and VCORE2).

As WA overwrite CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 0x1 (SW_SLEEP).

Change-Id: I2e453c07f61bab28a7213dd66044fd41a021961b
Signed-off-by: Arthur Cassegrain <a-cassegrain@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Patch Set 1

Signed-off-by: Dan Trifan <jimsth@gmail.com>
HSMMC:Set disable timeout to 1ms

The disable timeout is reduced from 100ms to 1ms in order
to obtain aggressive power saving.

Cherry picked from p-android-omap-2.6.35 commit ID:
50df9d10a9b33c82ad02003686050b12b03d4dfe

Change-Id: Ieaa47d51396e7b92f6c1ba71e62900c58a05a26c
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
MMC: OMAP HSMMC: Enable Auto CMD12

Configure OMAP HSMMC module to support Auto CMD12.
This will increase throughput during multi-block
command operations as CMD12 does not have to be
explicitly sent each time by software intervention.
Instead, hardware will send CMD12 after desired
number of blocks are transferred.

Change-Id: I37bf31399c80531d9fd76baa736a59a118c769b0
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
mmc: OMAP HSMMC: Add cmd23 support

Add support for set block count, close ended transfer

Change-Id: Iab7386e1171a42ebdf55306fbf291a3e6dd85b40
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
omap4-hsmmc : Adding ADMA support

Adds ADMA support for HSMMC controllers 1 & 2 on OMAP4
Ensure dma-sg list coming from block layer is unmapped after
every transfer completion.

Change-Id: I1b898f771a3119804920c5cd17ec9c4456c60916
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Signed-off-by: David Taylor <x0158378@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
mmc: omap: align adma and dma table entries

mmc->max_segs to core layer was set to 1024, but
adma table entry could only hold 512 entries. Increase
adma table entry size to 1024 from 512 to avoid mismatch.

Also set max_blk_count, max_req_size to what adma can
handle.

Change-Id: I8e08ee39bfa966bdf8a6c4374aea82b34fedcc62
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
mmc: omap: Increase number of blks we can handle

The above block layer is doing a "min" of max_req_size
and max_blk_count*512 before submitting each request.

As a result, the maximum size of request we are getting
is only 120*512 = 60KB even though each line in the
ADMA table can handle can handle that data alone.

So, we increase the max_blk_count we can handle. Also,
note that worst case is when above block layer gives
us 512 segments, in which there are 511 single block
entries, but one large block that is of size
mmc->max_req_size - (511*512) bytes.

In this case, we use the reserved 512 table entries
to break up the large request. Also adjust the
max_segs accordingly.

Change-Id: I733effdebea94f51a49bbf323950529afbb00dc4
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
omap-hsmmc: Implementation of i761 errata

Errata description:
Due to a bad behavior of an internal signal, the Card Error interrupt bit
MMCHS_STAT[28] CERR may not be set sometimes when an error occurred in the
card response.

Workaround:
After responses of type R1/R1b for all cards and responses of type R5/R5b/R6
for SD and SDIO cards, software must read two registers: MMCHS_RSP10 and
MMCHS_CSRE. When a MMCHS_CSRE[i] bit is set to 1, if the corresponding bit at
the same position in the response MMCHS_RSP10[i] is set to 1, the host
controller indicates a card error and software should proceed in the same way
as if a CERR interrupt would have been detected in the MMCHS_STAT register.

Note:
This errata is applicable for omap44xx.

Change-Id: Ib024bfb0624df04b7d6c61c129cbd9a34f919814
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: IVA AUTO RET relaxed workaround in idle path

AUTO RET for IVA VDD Cannot be permanently enabled during OFF mode due to
potential race between IVA VDD entering RET and start of Device OFF mode.

It is mandatory to have AUTO RET for IVA VDD exlusive with Devide OFF mode.
In order to avoid lockup in OFF mode sequence, system must ensure IVA
voltage domain transitions straight from stable ON to OFF.

In addition, management of IVA VDD SmartReflex sensor at exit of idle path
may introduce a misalignment between IVA Voltage Controller state and IVA
PRCM voltage FSM based on following identified scenario:

IVA Voltage Controller is woken-up due to SmartReflex management while
IVA PRCM voltage FSM stays in RET in absence of any IVA module wake-up event
(which is not systematic in idle path as opposed to MPU and CORE VDDs being
necessarily woken up with MPU and CORE PDs).

WA involves:
Ensure stable ON-OFF transition for IVA voltage domain during OFF mode sequence.
Ensure VCON and PRCM FSM are kept aligned due to IVA SR handling in idle path.
1) AUTO RET for IVA VDD is enabled entering in idle path, disabled exiting idle
   path and IVA VDD is always woken-up with a SW dummy wakeup.
2) OFF mode is enabled only in Suspend path.
3) AUTO RET for IVA VDD remains disabled in Suspend path (before OFF mode).

REVISIT: Update the patch once proper Errata is out for 44xx.

Benefits:
1) This patch ensures it is possible to gate SYS_CLK during OS-Idle LCD OFF
when all domains are idled, saving up to 2mA at VBAT from external clock buffer.

2) IVA voltage domain is now allowed to scale to Retention during idle which
reduces power consumption on all types of use case allowing extensive use of
idle path (e.g.: Home screen, Page reading). Effects are especially visible
if system uses Smart-Reflex Class 1.5 compared to Class 3 considering the
increased difference of voltage from converged Voltage SR vs Retention voltage.

TODO: quantify the actual savings from IVA-RET with further measurements.

Change-Id: I01f0431f7556f0baf0b5b6b42092cd11c2442f00
Signed-off-by: Cedric Vamour <c-vamour@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/pm44xx.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: OMAP4: EMIF: implementation of errata i735 for PM timer

EMIF Power Management timer for Self Refresh will put the external SDRAM
in Self Refresh mode after the EMIF is idle for number of DDR clock cycles
that is set with REG_SR_TIM. The minimal value starts at 16 cycles.
However due to Errata i735, the minimal value is 512 DDR cycles as it is
required at OPP100 frequency.

Change-Id: If0748903580877aa4c1803f47e9134ee60c1dd75
Signed-off-by: Konstantyn Shlyakhovoy <x0155534@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/emif.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
sched: LOAD_FREQ (4*HZ+61) avoids loadavg Moire. From http://ripke.com/loadavg/moire

Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: OMAP4: l2x0: Cleanup prefetch offset register setting

The bits [31:5] of Prefetch Offset Register are reserved in
PL310 r2p0 so they should be kept unchanged.
It's enough to set Data prefetch enable bit in PL310 auxiliary
control register to enable the feature, so setting of bit 28 of POR
is removed.
Before writing POR value, the bits [4:0] has to be cleared to remove
previous value.

Change-Id: Id5d047da0daa0c841c69d4d587d2280d2f3433f9
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>