cores/mor1kx: use 'version' instead of deprecated 'branch' option

When the the version option was introduced the branch option is
no longer recognised and will be ignored. Even though there is
a fallback to master when there is no version option stated,
explicitly stating it makes it more clear for users what to modify
to get a certain version.
cores: add diila - Device Independent Integrated Logic Analyzer core
cores: add wishbone to avalon bridge core

Core for bridging between wishbone and avalon busses.
Bursting is not yet supported.
wb_intercon: Add wb_intercon generator

wb_intercon_gen creates a verilog wrapper module that instantiates
wb_mux and wb_arbiter components to form an interconnect block.

As input, a configuration file is used for specifying masters, slaves
and their configurations.
wb_intercon: add generation of instantiation template

This make wb_intercon_gen generate a template instantiation of
the module it has created, with associated wires.
The template is generated in the form of a header file, which
is intended to be `included in the target design.
or1200-generic: use wb_intercon_gen template header file
systems: add minimal de0 nano board support

Supported peripherals are:
SDRAM, uart and debug_if.
Highest on TODO list is to add SPI, I2C and simulation support.
Lower on the list is to bring in support for LCD and touchscreen
add-on board.
Merge branch 'de0_nano' of https://github.com/skristiansson/orpsoc-cores
add .gitignore
cores: add altera_virtual_jtag core

Used as a wrapper to altera virtual jtag by advanced debug sys,
but isn't limited to that.
de0_nano: use common altera_virtual_jtag core
cores: mt48lc16m16a2: core is now fetched from micron's url

Import Micron's original file and add patches for:

- changing EOL from Dos to Linux,
- add an parameter to clear the SDRAM before it is used,
- add tasks to get/set bytes/sorts in the whole memory,
- turn off the debug messages.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge branch 'for-openrisc' of https://github.com/skristiansson/orpsoc-cores
cores: mt48lc16m16a2: change MEM_SIZES to lower case in patch 0004

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: adv_debug_sys: For X to zero during sim in crc module

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_intercon: assert wbm_err_o on non-match accesses

Instead of falling back to the first slave when no match occur,
signal a wishbone error. If fallback behaviour is desired,
it's still acheivable by extending the range of the slave
to which the fallback is desired.
avalon_to_wb_bridge: abort read on wbm_err_i
cores: add vga_lcd core

This adds the vga_cld core from opencores, with two accompanying
patches.
One for a typo of a signal and one for fifo auto resync.
Merge pull request #12 from fjullien/for-upstream-new

cores: adv_debug_sys: Force X to zero during sim in crc module
Merge pull request #13 from skristiansson/for-openrisc

cores: updates fixes and additions