Tweak filter_xml_frames. Suppress frames containing neither a
function name nor any source code reference.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13559 a5019735-40e9-0310-863c-91ae7b9d1cf9
mips32/mips64: tests for FCSR.

Change the existing tests to print the value of the FCSR
register after the mips fpu instruction is executed.
Add tests that are testing the value of FCSR register.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13560 a5019735-40e9-0310-863c-91ae7b9d1cf9
Fix memory leak when reallocating a thread name.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13561 a5019735-40e9-0310-863c-91ae7b9d1cf9
The patch fixes the assembly of the Power dcbtst and dcbt instructions.

The assembly of these instructions is not alwasy being done correctly as
described in the following email reply.

  Re: Assembling Power instructions: dcbtst/dcbt.

      From: Peter Bergner <bergner at vnet dot ibm dot com>
      To: Paralkar Anmol-B07584 <B07584 at freescale dot com>
      Cc: "amodra at bigpond dot net dot au" <amodra at bigpond dot net dot au>, "binutils at sourceware dot org" <binutils at sourceware dot org>
      Date: Fri, 13 Sep 2013 15:22:35 -0500
      Subject: Re: Assembling Power instructions: dcbtst/dcbt.
      Authentication-results: sourceware.org; auth=none
      References: <DC6D7B34688246489A6578981A5ADEB9302A07 at 039-SN2MPN1-012 dot 039d dot mgd dot msft dot net>

  On Fri, 2013-09-13 at 18:32 +0000, Paralkar Anmol-B07584 wrote:
  > Hello,
  >
  >  Per Power ISA Version 2.07 (May 3, 2013) "4.3.2 Data Cache Instructions",
  >  the assembly language syntax for the dcbtst instruction (pp. 771) is:
  >
  >  dcbtst RA,RB,TH [Category: Server]
  >  dcbtst TH,RA,RB [Category: Embedded]
  >
  >  and it's layout in the object code is:
  >
  >   +------+------+------+------+------------+---+
  >   |  31  |  TH  |  RA  |   RB |  246(0xF6) | / |
  >   |0     |6     |11    |16    |21          |31 |
  >   +------+------+------+------+------------+---+
  >
  >  (Analogously: dcbt pp. 770)
  >
  >  However, GAS (as of version 2.23.52.20130912) decides on the syntax to use based on
  >  processor/architecture dialect (not Power ISA Category), using the Server syntax in
  >  the case of POWER4 and the Embedded syntax for generic PPC or VLE.

  That was a bug fixed here:

      https://sourceware.org/ml/binutils/2012-11/msg00352.html

  >  Consequently (e.g.),
  >
  >  dcbtst 17, 14, 6
  >
  >  in the assembly file gets "misassembled" under -many for a user-space program on Linux:

  When you only specify -many (and not one of -mpower4, -mpower5, etc.),
  the assembler/disassembler will choose a default -m<CPU> value for
  you.  That has changed over time, but is generally one of the newer
  server cpus.  For example, for binutils trunk, the default is now
  -mpower8 and for your 2.23.x binutils, it is -mpower7.
  That should force the assembler and disassembler to assemble
  the instruction using the server operand order you want, but the bug
  above (which is in 2.23) basically resets it to an old cpu, so it
  chooses to use the embedded/old cpu setting.

The patch from Amodra fixes the issue by manually generating the correct
hex value for the instruction rather then leaving it to the assembler to
generate the hex value from the symbolic assembly instruction name.

This is the fix for Bugzilla 324765.  

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13562 a5019735-40e9-0310-863c-91ae7b9d1cf9
Oops, commit 13562 said the patch was done by Amodra.  It should have
said the patch was from Paralkar Anmol.

This is the fix for Bugzilla 324765.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13563 a5019735-40e9-0310-863c-91ae7b9d1cf9
Move some now-closed bugs into NEWS.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13564 a5019735-40e9-0310-863c-91ae7b9d1cf9
Recent libxul.so on ARM has more than 5000 CIEs.  Increase N_CIEs,
therefore.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13565 a5019735-40e9-0310-863c-91ae7b9d1cf9
Comment-only change.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13566 a5019735-40e9-0310-863c-91ae7b9d1cf9
Increase VG_N_SEGMENTS and VG_N_SEGNAMES by a factor of 6 on all
non-{phone/tablet} platforms.  Possibly fixes #164485.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13567 a5019735-40e9-0310-863c-91ae7b9d1cf9
Double the size of the (already huge) translation cache on all
non-phone/tablet targets.  The previous apparently-huge sizing is
evidently not huge enough for recent apps, eg, recent Firefox requires
circa 350k translations to get started and almost fills an 8-sector
cache merely starting up and then idling.

On Android targets, fall back to 6 sectors; space is critical.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13568 a5019735-40e9-0310-863c-91ae7b9d1cf9
mips32/64: add extra test cases in vbit-test for mips32/64.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13569 a5019735-40e9-0310-863c-91ae7b9d1cf9
Add a script 'check_headers_and_includes' to check that #include directives
are not against the grain.
Wrap this script together with 'check_makefile_consistency' into
'post_regtest_checks' and invoke that from the toplevel Makefile. So we can
easily add new checkers in the future.

Add a new make target 'post-regtest-checks' to just run those checks
and nothing else.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13570 a5019735-40e9-0310-863c-91ae7b9d1cf9
Fix two issues found by check_headers_and_includes.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13571 a5019735-40e9-0310-863c-91ae7b9d1cf9