sha1: code cleanup and use modern C syntax

Apply the following changes:
- Remove out-of-date workaround (SPARC64_GCC_WORKAROUND)
- Use C99 prototype and stdint type

Change-Id: I630cf97f6824f72f4165e0fa9e5bfdad8edabe48
Add ARMv7 optimized strlen()

Merge the ARM optimized strlen() routine from Linaro.  Although it is
optimized for ARM Cortex-A9, the performance is still reasonably faster
than the original on Cortex-A8 machines.

Reference benchmark on Nexus S (ARM Cortex-A8; 1 GHz):

[before]
             prc thr   usecs/call      samples   errors cnt/samp     size
strlen_1k      1   1      1.31712           97        0     1000     1024

[after]
             prc thr   usecs/call      samples   errors cnt/samp     size
strlen_1k      1   1      1.05855           96        0     1000     1024

Change-Id: I809928804726620f399510af1cd1c852ed754403
memcmp: prefetch optimizing for ARM Cortex-A8/A9

The original memcmp() was tweaked for ARM9, which is not optimal for ARM
Cortex-A cores.  This patch merges the prefetch optimizations from
ST-Ericsson and removes NEON slowdowns.

Reference experiement results on Nexus S (ARM Cortex-A8; 1 GHz) using
strbench program:
    http://pasky.or.cz//dev/glibc/strbench/

[before]
size, samples, TIMES[s] - user, system, total)
   4   262144         2.510000 0.000000 2.510000
   8   131072         1.570000 0.010000 1.590000
  32    32768         1.310000 0.000000 1.320000

[after]
size, samples, TIMES[s] - user, system, total)
   4   262144         2.280000 0.000000 2.290000
   8   131072         1.210000 0.000000 1.220000
  32    32768         1.040000 0.000000 1.050000

Change-Id: I961847da96d2025f7049773cd2ddaa08579e78d6
fix ARMv7 optimized strlen() usage condition

Change-Id: Ia2ab059b092f80c02d95ca95d3062954c0ad1023
getopt(): fix missing carriage return on bad parameters

This affect all command line tools which show the usage on stdout
after an invalid parameter error (printed on stderr)

Change-Id: I8e2cb3fda241ab989dc42055f15082f8b3ba1397
Signed-off-by: Tanguy Pruvot <tanguy.pruvot@gmail.com>
headers: Unbreak some ARM syscalls

Restore the outside-kernel exclusion for some syscalls that was
removed by change I959b64280e184655ef8c713aa79f9e23cb1f7df4,
since these syscalls are used elsewhere.

Change-Id: I5b5bf3d78edd137e820d25281a375966b6c009ec
Bionic/libm: fast neon pow() for small x,y

Add a fast neon version of pow() suitable for relatively small
positive x and y (between 0 and 4).  Run the standard
implementation in all other cases.  Gives approximately 60%
performance improvement to AnTuTu FPU score.

Change-Id: I9234d37eaa6a815d1e619375f5b049c4ec88f557
armv6: REX routines are currently broken, use alternatives

Change-Id: I7ac05ab6add7802a4cc24fe36f7181e7cdfe07e0
Bionic/libm: Prefer branches and VFP ABI

For internal functions set gcc attribute "aapcs-vfp" for ARM
and use -fno-if-conversion to prefer branches over predicated
instructions (improves performance on architectures with good
branch prediction).

Change-Id: I365e9508bd3babb0bb06fc5de127c1ae17445bcc
Add missing define to build qcom libgralloc.

This is needed by hardware/qcom/display/libgralloc/ashmemalloc.cpp.

Change-Id: I7b35bcdaedf3874d17a0e6ce18931c11db1e133d
Add missing define to build qcom libgralloc.

This is needed by hardware/qcom/display/libgralloc/pmemalloc.cpp

Change-Id: Id0732b82ed6c1852def9688544ec92e04afeff00
Add missing define for libcopybit.

This is needed by hardware/qcom/display/libcopybit/copybit.cpp.

Change-Id: Ic50a75b93b39443b772dd4cab67a55f75ad2b5ad

Conflicts:
	libc/kernel/common/linux/msm_mdp.h
linker: restore prelink support

Prelink support is required to load old vendor binary blobs
on many devices properly

This commit partially reverts 4688279db5dcc4004941e7f133c4a1c3617d842c

Change-Id: Ibc835095579c0bbd18aff61f37bd420de353e94d
bionic: Optimizations for gettimeofday and clock_gettime.

Use the kernel user helper feature to calculate the results
of gettimeofday and clock_gettime without actually calling
into kernel space. If the user helper patches have not been
applied to the kernel, the regular system calls are used as
a fallback.

Change-Id: I3aebc6ac19ab4743725648a1a279819e624cc5c4
Add optimized version of memcpy for Cortex A9

Adds new code to memcpy function, optimized for Cortex A9.
Adds new ARM-only loop, for operations where source and
destination are aligned.

Copyright (C) ST-Ericsson SA 2010

Modified neon implementation to fit Cortex A9 cache line size,
for those running 32 bytes L2 cache line size.
Also split the implementation in aligned and unaligned access,
for those that allows unaligned memory access with Neon.
For totally aligned operations, arm-only code is used.

Change-Id: I95ebf6164cd6486b12a7e3e98e369db21e7e18d2
Author: Henrik Smiding henrik.smiding@stericsson.com for ST-Ericsson.
Signed-off-by: Christian Bejram <christian.bejram@stericsson.com>
Fix perf regression on Cortex A15 by optimized memcpy for Cortex A9

The new Cortex A9 optimized memcpy included an arm-only version that is
slower than the current neon Cortex A15. This arm-only version was used
when the dst was aligned to an 8 byte boundary, otherwise, the original
neon only version was used. This change modifies the code so it always
uses the neon only version for the Cortex A15. It also fixes the use of
a define removed with the previous optimization.

Change-Id: I971527568a177218cd8b76a8bd160aaaf6ea1e42