Remove SPI Clock divider limitation

The limitation have been based on this staement in the BCM2835 ARM Peripherals datasheet page 156:

CLK Register
Synopsis: This register allows the SPI clock rate to be set.

Bit(s)  Field Name   Description
15:0     CDIV         Clock Divider
                      SCLK = Core Clock / CDIV
                      If CDIV is set to 0, the divisor is 65536. The
                      divisor must be a power of 2. Odd numbers
                      rounded down. The maximum SPI clock rate is
                      of the APB clock.

Testing has shown the driver to work without this limitation:
http://www.raspberrypi.org/phpBB3/viewtopic.php?f=44&t=43442