[FIX] Fix write and read delay of DPRAM components

The DPRAM available in the library is fixed to the following access
latency. All architecture shall follow this specification!
write/read = 0/1 [cycles]

Change-Id: I05c74af47d8ad64bdb5234687bc14651de599d91
Reviewed-on: http://brateggevoat1/gerrit/1375
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix Altera DPRAM instantiation

Delete the default generic assignments of the altsyncram instantiation.

Change-Id: Iac0a2cc08a7e8a1844e7a2149958db641973ec63
Reviewed-on: http://brateggevoat1/gerrit/1376
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Add holdoff state to bus master model

This enables activating the bus master model at a later point in the
simulation run.

Change-Id: I74c9e477f4db413ae7abb7e8fcb4180b0bbd880d
Reviewed-on: http://brateggevoat1/gerrit/1377
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Cleanup of hostinterface vhdl sources

- Align assignments
- Delete component declaration
- Doxygen comments

Change-Id: Ib7d41ffe4615c9d82da10e3e1c90417c7fefbee1
Reviewed-on: http://brateggevoat1/gerrit/1378
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Exchange revised component library in host interface

Use revised components:
- address decoder
- synchronizer
- edge detector

Change-Id: I7f97a02532fc37dd2d7888a3b2ae062edf7f5096
Reviewed-on: http://brateggevoat1/gerrit/1379
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Rework host interface bridge instance

- Add reworked bridge instance (named dynamic bridge)
- Remove obsolete magic bridge
- Store dynamic translation offsets in logic or memory resources
- Break worst case timing path in address translation arithmetic

Change-Id: I136aeba9895ac26237e88cfe52295fd4064cfa2e
Reviewed-on: http://brateggevoat1/gerrit/1380
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Cleanup of Altera host interface toplevel

- Set address translation storage to M9K resources

Change-Id: I6d425169c0a7995c78b02da77c05eddcfa626937
Reviewed-on: http://brateggevoat1/gerrit/1381
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Update host interface ipcore version to V0.0.4

Change-Id: If712e701ea8bffbf853e4dfc72c3aab3e94530c8
Reviewed-on: http://brateggevoat1/gerrit/1382
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>