Missed removing one of the assert()'s from the LLVMCreateDisasmCPU() library
API with my 176880 revision.  If a bad Triple is passed in it can also assert.
In this case too it should just return 0 to indicate failure to create the
disassembler.

rdar://13955214


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182542 91177308-0d34-0410-b5e6-96231b3b80d8
Updated the comments of APInt.h to match the llvm style guide and be consistent. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182555 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182556 91177308-0d34-0410-b5e6-96231b3b80d8
[objc-arc] Fixed number of prefixing slashes in some comments in a function from 3 to 2 to match the rest of ObjCARCOpts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182557 91177308-0d34-0410-b5e6-96231b3b80d8
Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182558 91177308-0d34-0410-b5e6-96231b3b80d8
Remove redundant rpath.

These are not needed since we added the $ORIGIN based rpath.

Fixes pr12517.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182559 91177308-0d34-0410-b5e6-96231b3b80d8
clang-format this file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182560 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a leak on the r600 backend.

This should bring the valgrind bot back to life.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182561 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing test from r175092.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182564 91177308-0d34-0410-b5e6-96231b3b80d8
Fix 32 bit build in c++11 mode.

The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
        MI.getOperand(6).getImm() & 0x1F,

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182584 91177308-0d34-0410-b5e6-96231b3b80d8
Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182585 91177308-0d34-0410-b5e6-96231b3b80d8
InlineSpiller: Store bucket pointers instead of iterators.

Lets us use a SetVector instead of an explicit set + vector combination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182586 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Hide symbols of implementation details.

Also removes an unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Make helper functions static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182588 91177308-0d34-0410-b5e6-96231b3b80d8
More symbols that should be static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182590 91177308-0d34-0410-b5e6-96231b3b80d8
Fix PR16110: Handle DBG_VALUE in ConnectedVNInfoEqClasses::Distribute().

Now that the LiveDebugVariables pass is running *after* register
coalescing, the ConnectedVNInfoEqClasses class needs to deal with
DBG_VALUE instructions.

This only comes up when rematerialization during coalescing causes the
remaining live range of a virtual register to separate into two
connected components.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182592 91177308-0d34-0410-b5e6-96231b3b80d8
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg

Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Add Performance Monitor Extensions feature

Performance monitors, including a basic cycle counter, are an official
extension in the ARMv7 specification. This adds support for enabling and
disabling them, orthogonally from CPU selection.

rdar://problem/13939186

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182602 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: implement @llvm.readcyclecounter intrinsic

This implements the @llvm.readcyclecounter intrinsic as the specific
MRC instruction specified in the ARM manuals for CPUs with the Power
Management extensions.

Older CPUs had slightly different methods which may also have to be
implemented eventually, but this should cover all v7 cases.

rdar://problem/13939186

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8