[opb_dram_sniffer] added transfer states to opb state machine in mem_opb_attach.v

Looking at timing diagrams for OPB protocol I noticed through simulation that given the timing of OPB_select and Sl_xferAck, the code as it was triggered an extra read operation after OPB_select goes low.  This should not be the case, and adding an extra clock cycle via a transfer state corrects for this.  In testing a compiled design this change appears to lead to better performance but does not correct for all of the misbehavior.  Namely, there is a place where the reading operation hangs in the opb state READ and the DDR3 state WRITE.  Puzzling as this should only occur (as the code is written, to my current understanding) with OPB_RNW set to 0.