i965/fs: Don't perform CSE on inst HW_REG dests (unless it's null)

Commit b16b3c87 began performing CSE on CMP instructions with null
destinations. I relaxed the restrictions a bit too much, thereby
allowing CSE to be performed on instructions with, for instance, an
explicit accumulator destination.

This broke the arb_gpu_shader5/fs-imulExtended shader tests because
they emit MUL instructions with the accumulator as the destination. CSE
would instead cause the MUL to write to a GRF, which is lower precision
than the accumulator.

Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: 10.0 <mesa-stable@lists.freedesktop.org>
glx: conditionaly build dri3 and present loader (v3)

This patch makes it possible to disable DRI3 if desired.

Tested with:

./configure --disable-dri3 --with-dri-drivers=i965 \
--with-gallium-drivers= --disable-vdpau --disable-egl \
--disable-gbm --disable-xvmc

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71397
Cc: 10.0 <mesa-stable@lists.freedesktop.org>
i965: Make the driver compile until a proper libdrm can be released.

No depending on unreleased code.
glsl: fix missing breaks in equals(ir_texture,..)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>