Merge pull request #71 from smirolo/master

links to bootcamp videos
Correct polarity of `ifdef SYNTHESIS guard
Fix BlackBox null pointer dereference

...by keeping a global list of BlackBoxes, rather than per-Module.
Fix BlackBox functionality

- Don't emit Verilog for BlackBoxes
- Treat BlackBoxes as regular Modules for C++ to support behavioral models
Make BlackBox Verilog module text the empty string
added different place for transformations, fix up isEnable for C backend
Merge branch 'master' of github.com:ucb-bar/chisel
fix margins and title
merge
missing fig
Supply BigInt constructors for Bits/UInt/SInt
Implement SInt/UInt order operators correctly

Before they converted the UInt operand to -2^n plus its value.
(How did this fall through the cracks for two years?)
Remove questionable Node => SInt conversion function
Remove isSigned property of Node

This notion presupposed that all types are integral, and it made the backend
logic more complex.  Signed operators like >> on SInt now are treated as
different operators entirely from their unsigned counterparts.
Remove > and >= operators from backends

They become < and <=, with the operands swapped, in the frontend.
Turn u%s and s%u operators into s%s under the hood

Before, we were emitting syntactically incorrect Verilog.
Update test cases to reflect removal of isSigned
Fix Mem with unconditional read enable

This also removes some old Mem-related cruft.
Dumping vcd before clock_hi is the most logical choice. Recall, the logic of clock_lo ensure that after its execution all signals are 'consistent' (ready to be clocked in, etc.) according to the current state and inputs whereas clock_hi just updates registers. This change is consistent with how the reference-chip testbench is constructed.
module c++ backend