target-s390: Disassemble more z10 and z196 opcodes

Also fix disassembly for COMPARE AND BRANCH.  The table must be
sorted by primary opcode, and several were out of place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Fix disassembly of cpsdr

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Fix gdbstub

The real gdb protocol doesn't split out pc or cc as real registers.
Those are pseudos that are extracted as needed from the PSW.  Don't
modify env->cc_op during read -- that way lies heisenbugs.

Fill in the XXX for the fp registers.

Remove duplicated defines in cpu.h.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Add missing temp_free in gen_op_calc_cc

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Use TCG registers for FPR

At the same time, tidy other usages of tcg_gen_deposit_i64.
In some cases we can "type cast" rather than extend, and in
others we can allow tcg_gen_deposit_i64 itself to optimize
the HOST_LONG_BITS==32 case.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Register helpers

Which highlights a lot of cc helpers that no longer exist.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Fix SACF exit

DISAS_EXCP is exit via exception; we wanted DISAS_JUMP.
This matters when we start cleaning up the TB exit paths.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Fix BCR

There were are two exit paths for which we forgot to
copy s->cc_op back to the tcg register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Tidy unconditional BRCL

Yes, we're about to rewrite all of this, but having this unconditional
jump recompute cc_op is a large source of "false diff errors" when
trying to examine before and after dumps.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Fix PSW_MASK handling

We were treating psw.mask as the 32-bit quantity it is in ESA mode.
In particular, the CC field was at the wrong place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Add format based disassassmbly infrastructure

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Split out disas_jcc

Lots of duplicated code replaced with a couple of tables.  We no longer
attempt to manually invert the logic operation: the comments now match
the code.  In the fully general test, constant propagate (1 << (3 - cc))
into (8 >> cc).

The new function will be usable by non-branch insns as well.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Reorg exception handling

Make the user path more like the system path.  Prepare for more kinds
of runtime exceptions.  Rename ILC to ILEN to make it clear that we
want to pass around a full instruction length, rather than a "code"
that happens to be stored one bit left in a larger field.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Convert ADD HALFWORD

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Implement SUBTRACT HALFWORD

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Convert MULTIPLY HALFWORD, SINGLE

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Convert 64-bit MULTIPLY LOGICAL

Use a new "retxl" member of CPUS290XState to return the "eXtra Low" part
of a 128-bit value.  That said, this will get used when two independent
values need returning (e.g. quotient+remainder) as well.

At the same time, shuffle the elements of CPUS390XState to get this new
space from existing padding in the structure.

Signed-off-by: Richard Henderson <rth@twiddle.net>
target-s390: Convert AND, OR, XOR

Signed-off-by: Richard Henderson <rth@twiddle.net>