Add comment with link to important github thread about sceSas threading
Add small ARM perf experiment. Did not help on ARMv7 so turned it off.

xsacha might want to try it on ARMv6.
This variant didn't seem to make much difference either (see prev commit)
Optimize mfv/mtv/mfc1/mtc1 on x86 too
Fix bug from a couple of commits ago in ARMJit
x86 jit: Rename BindToRegister to MapReg
ARM regcache: Add mechanism to keep registers converted to pointers around
Add experimental mode to cache pointers in the arm jit.

Turned off for now as it needs more work but seems quite promising already.
armjit: Preserve imms on min/max as well.
armjit: optimize reverse subtract, avoid temp imms.

If we have a non-op2 imm, get rid of it asap.  If we have a op2 friendly
imm, keep it.
armjit: Improve GPR typesafety.
armjit: Allocate regs in preferred slots.

This may allow better flushing.  Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
armjit: Flush regs using STMIA where possible.
armjit: Clean up some magic numbers.
Remove erroneous comment.
Merge pull request #4480 from unknownbrackets/perf

Flush regs using STMIA if possible, plus imm adjustments (armjit)
armjit: Handle lwl/lwr (not pretty, though.)
armjit: Use multiple BICs in ANDI2R if possible.

Rather than a temporary.
armjit: Optimize lwl/lwr against an imm address.
armjit: Implement msub/msubu.