Import migen and mibuild as submodules
ovctl: Implement -C flag to exit after loading bitstream
Blink-a-led with migen/mibuild and OV3 platform definition.
Add PLL to generate system/SDRAM clocks
Initial skeleton SDRAM FIFO module (initialization only)
Implement refresh cycles
First shot at SDRAM controller (doesn't work properly yet)
Add simple SDRAM testbench
Make SDRAM work: reads are NOT one cycle beyond tCL after all.
Add ULPI (+Sim), not yet wired up
Add *.vcd to .gitignore
Add ULPIRegTest, a synthesizable test for the register interface
Wire up ULPI in toplevel module
ulpi hack: un-delay outputs