soc/cpu: externalize the reset.

Allow the debug controller generated reset signal to also reset SoC
peripherals.
rtl: save the PSR at the correct time.

For exceptions raised at the fetch stage we need to save the PSR, but
there could be instructions in the decode + execute stage so don't save
the PSR until those are clear of the execute stage.
sim: construct PSR when reading control registers.

Convert our internal representation of the PSR to the programmers model
view on demand.