Internals: Move VARRESET rule to match Verilog-Perl and prevent next change conflict, towards bug586. No functional change.
Internals: Remove VAR_MEM to match Verilog-Perl, towards bug586.
Fix implying dotted wire names
Internals: Add V3LinkDot m_ds structure, towards bug586. No functional change.
Fix package resolution of parameters, bug586.
Test added
Copyright year update.
Fix task inlining under case values, bug598.  Note this reorders high level operations, so may change loose some optimizations.
Fix package import preventing local var, bug599.
Merge branch 'master' into verilog-short-circuit