drm/i915: reject tiling for objects smaller than their tile row size

For these objects there isn't enough backing storage even for a single
linear pixel line, so asking tiling for them is clearly a programming error.

i915_gem_get_tile_row_size() will be used by a later patch, so export it.

In v3:
- don't use PAGE_SIZE for the tile size as this is only coincidental and
  for Gen2 not even true (Chris Wilson)
- use the correct tile size of 2048 bytes for Gen2 (Chris Wilson, Daniel
  Vetter)

Signed-off-by: Imre Deak <imre.deak@intel.com>
drm/i915: check tile object alignment explicitly

So far we used the object size for alignment check, since this matched
the actual alignment requirement. An upcoming patch will introduce
linear and physical fenced sizes making this connection less clear, so
use instead the get-alignment function explicitly.

Signed-off-by: Imre Deak <imre.deak@intel.com>
drm/i915: fix gtt space allocated for tiled objects

The GTT space needed for tiled objects might be bigger than the linear
size programmed into the correpsonding fence register. For example for
the following buffer on a Gen5+ HW:

- allocation size: 4 * 4096 bytes
- tiling mode: X tiled
- stride: 1536

This needs 6 * 4096 bytes of GTT space to cover all the pixels in the
buffer, but at the moment we allocate only 4 * 4096. This means that any
buffer following this tiled buffer in the GTT space will be corrupted if
pixels belonging to the last two tiles are written.

Fix this by limiting the linear size to the object's last full tile row
offset (3 * 4096 bytes in the above example). Beyond this offset we
don't have enough backing storage to hold even a single linear pixel
line, so tiling wouldn't work properly anyway. For old HW with
power-of-two fence regions we might have to also overallocate GTT space
in case the POT offset happens to be not aligned to the tile row size.
The page frames for the overallocated area will be backed by the single
GTT scratch page used already for padding objects with a POT fence
region.

Note that this is more of a security/robustness problem and not fixing any
reported issue that I know of. This is because applications will normally
access only the part of the buffer that is tile row size aligned.

In v2:
- Instead of always overallocating for unaligned objects, limit the
  linear size - and overallocate only when necessary for POT fence
  sizes. Discussed this with Chris Wilson.
- Force buffer-rebind if the GTT size changes after a tiling change.
  (Chris Wilson)

Signed-off-by: Imre Deak <imre.deak@intel.com>