Live-in copies go *after* EH_LABELs.

This will soon be tested by exception handling working at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185615 91177308-0d34-0410-b5e6-96231b3b80d8
FastISel can only apend to basic blocks.

Compute the insertion point from the end of the basic block instead of
skipping labels from the front.

This caused failures in landing pads when live-in copies where inserted
before instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185616 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be  scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185617 91177308-0d34-0410-b5e6-96231b3b80d8
Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185618 91177308-0d34-0410-b5e6-96231b3b80d8
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.

These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
Supporting ssize_t on WIN64 with its proper size.  Patch thanks to David Cournapeau!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185627 91177308-0d34-0410-b5e6-96231b3b80d8
SimplifyCFG: Teach switch generation some patterns that instcombine forms.

This allows us to create switches even if instcombine has munged two of the
incombing compares into one and some bit twiddling. This was motivated by enum
compares that are common in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185632 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Add asm parser support for CR expressions

This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Add all trap mnemonics

This adds support for all basic and extended variants
of the trap instructions to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.

This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185651 91177308-0d34-0410-b5e6-96231b3b80d8
Changing long to int for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185656 91177308-0d34-0410-b5e6-96231b3b80d8
Add 'not' in front of a command that is expected to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Implement writeNopData

This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.

This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
Fix leak. Should bring back the valgrind bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185663 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for archives with no symbol table or string table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185664 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Reimplementation of visitUDivOperand

This transform was originally added in r185257 but later removed in
r185415.  The original transform would create instructions speculatively
and then discard them if the speculation was proved incorrect.  This has
been replaced with a scheme that splits the transform into two parts:
preflight and fold.  While we preflight, we build up fold actions that
inform the folding stage on how to act.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185667 91177308-0d34-0410-b5e6-96231b3b80d8
MC: Add .section directive to COFF

Supports GAS flags "abdnrswxy". No support for alignment or subsections.

Fixes PR16366.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185669 91177308-0d34-0410-b5e6-96231b3b80d8
Initialize object file info before output streamer

r179494 switched to using the object file info to retrieve the default text
section for some MC streamers. It is possible that initializing an MC
streamer can request sections before the object file info is initialized
when the AutoInitSections flag is set on the streamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185670 91177308-0d34-0410-b5e6-96231b3b80d8