msm: cache_erp: Handle recoverable L1 errors

Some CPU designs may be able to recover from certain types
of L1 instruction cache errors. Rather than panicing
whenever any kind of L1 error is encountered, add an option
to selectively panic on recoverable L1 errors

Change-Id: Id8beb0e58d41fa5319f4ca76c5f35e2162f8b704
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit e1aba3d9b510d34e8309669d811a6f01568858dc)

Conflicts:

	arch/arm/mach-msm/Kconfig

Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/cache_erp.c

Conflicts:

	arch/arm/mach-msm/cache_erp.c

 Author:    Stepan Moskovchenko <stepanm@codeaurora.org>
	modified:   arch/arm/mach-msm/Kconfig
	modified:   arch/arm/mach-msm/cache_erp.c
Merge branch 'asdk-4.1' of git://github.com/Ayysir/ASDK-sgs2 into asdk-4.1