This patch mostly implements some of the finalizing features for the IBM-PC
SMP mode switch transition. Also straightens out some bugs in the LAPIC/IO-APIC
init code and brings all emulators and real hardware up to date and working
with the kernel.

A few minor bugs were found and fixed here and there, as always.

* Bus-Pin Mappings: Now loading the Bus-pin mappings for a bus also programs the
  IRQ Controller pins for that bus alongside obtaining the information on which
  devices on the bus pertain to which pins. The ISA case has already been
  implemented.
* Timer Queues: When the chipset registers a clock routine on a timer queue,
  that queue is automatically enabled and soft-disabled if it isn't currently
  in use.
* ZKCM: Implemented a new ZKCM_ISR_SUCCESS_AND_RETIRE_ME ISR return value.
* IBM-PC:
  * ZKCM CPU Detection Mod: getBspId: If the BSP CPU has no LAPIC, we assign it
    a fake ID of 0.
  * i8254 PIT:
    * Improved locking in the ISR for the finalizing IRQ case.
    * Removed the buggy retirePinIsr() call, and replaced it with the new
      ZKCM_ISR_SUCCESS_AND_RETIRE_ME feature.
    * Improved state machine manipulation for the ISR registration and the IRQ
      status tracker.
    * Fixed a race condition in slow emulators and on slow hardware where the
      kernel could stop executing altogether when doing the SMP mode switch by
      increasing the finalizing IRQ timeout when the SMP mode switch is in
      progress.
  * ISA Bus-Pin Mappings:
    * SMP-mode BPM:
      * Now all ISA IO-APIC pins are set to a default state when BPM is being
        executed: Edge-triggered, rising, physical dest mode, fixed delivery
        mode, BSP CPU, vector = vectorBase+<N>.
      * Improved readability, separation, re-use and genericity of the code.
* x86-32:
  * IO-APIC:
    * IO-APICs are now mapped into the kernel addrspace as uncacheable.
    * setPinState() now preserves the masking status of the pin in question.
    * Added register index checking to IO-APIC register windowing.
  * Local APICs are now mapped as uncacheable.
* Interrupt Tributary:
  * Implemented the new ISR-retire infrastructure for ISRs that wish to be
    retired while being executed.
  * Improved atomicity of ISR execution.