msm: kgsl: Don't do intensive memory recovery when allocating big pages

We don't want to incur too much overhead when allocating big pages
so don't attempt to retry, perform reclaim, or run memory compaction
on high-order allocations.

Change-Id: Ic0dedbadb354c6faea34abec36aee268ac0f2c34
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Insert kgsl idle for iommu-v1 when pagetables are changed.

An idle is needed for iommu-v1 before programming both tlb registers
and the pagetable register. Without this idle faults are observed on
2D core because a process uses another processes pagetable.

Change-Id: Ief14cd79b8e7ffaed413da49dc4b9e8416233186
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Don't access context memory after it's freed

Context memory was potentially accessed after being freed. Fix this
by incrementing the context's refcount at strategic places.

Change-Id: I31049bdd3eb9ac52160ca593619fcc8a32d4ddee
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
msm: kgsl: Add NULL check for next_event hook

KGSL driver needs to check that the function pointer
is not NULL before calling the hook. next_event
is an optional function not implemented by the 2d
core. This fix ensures that optional and unimplemented
function will not invoked by the driver.

Change-Id: I687b028260e3ec304d973c6a5bded0a8fdbfb73b
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Don't consider active count if not in active state

Don't consider active_cnt variable if not already in ACTIVE state.
The active count variable does not necessarily exactly indicate the
number of open handles to GPU for switching power state. Hence,
only wait for active count to reach zero before switching to SUSPEND
state if, the current state is ACTIVE.

CRs-fixed: 483154
Change-Id: Ie025a1873cfb9237bdfba89204f4c2116549eba4
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
gpu: msm: Allow retries for 0 order allocation

When allocating order 0 pages we allow the allocator to retry
the allocation to ensure we can take advantage of pages that
are being reclaimed. This will help avoid unnecessary out
of memory errors from kgsl clients.

Change-Id: Iec2a0a1fe10302c320a58cef90ae1ee7e35d71ee
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
msm: kgsl: Remove ts_notifier_list

Remove ts_notifier_list from the driver since it is not being
used and is causing extra work to be done in the interrupt
handlers for A2XX, A3XX and Z180.

Change-Id: I5512e36f1e807f3a3e62aeac54cfd3075d4cf7a4
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
msm: kgsl: Remove extra interrupts when setting MMU state

The interrupts added to the ringbuffer on PTFLUSH and TLBUPDATE
were causing a major increase in the number of interrupts from the GPU.
This was leading to increase in power and loss of performance. Add a check
to turn off IOMMU clocks when going to SLEEP.

Change-Id: I41617dd3b7b3f7d9622523f2a1407b912dbd989e
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: use readonly mappings on the iommu

Userspace passes a flag KGSL_MEMFLAGS_GPUREADONLY when
the gpu should not write to a memory region. Use this
flag to control IOMMU_WRITE permissions on the buffer.

Change-Id: I5d3fc615dc36687252e2242f63fe74d6ce1c4fbc
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: clean up use of memdesc->hostptr

Some external memory types were using hostptr to store
a userspace virtual address, but other code assumes it is a
kernel virtual address. Make memdesc->hostpr always
be the kernel virtual address and add a useraddr
field for the userspace virtual address.

Change-Id: Id4580a2ff34aeb15f2c1b26a7134f0fd4ec52a6e
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: prevent multiple or partial mmaps of a buffer

These cases have never been a normal operation pattern of the
userspace driver. Sharing buffers through multiple mappings
is better left to dma-buf or ion.

Change-Id: I7e7658137937c96b9505d0f912dcb262d652e0c3
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: disable use of iommu TTBR1

The v1 iommu only supports splitting between TTBR0 and TTBR1
on a power of two boundary. Cutting off the userspace address
at 2G (0x80000000) is inconvienient, as the GPU userspace
address space should align with the CPU address space.

This requires changing how global allocations are managed,
since there is no longer a separate pagetable for TTBR1.
The default pagetable is still the master of these allocations
and maintains the gen_pool for allocating global addresses.
But now, these regions are mapped into each process pagetable
by calling kgsl_setup_pt(). This requires kgsl_mmu_map
and kgsl_mmu_unmap to be able to handle mapping without
virtual address allocation.

Change-Id: I94e2d63dc7e6a7ef576f993770725b6b7ba14228
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: add IOCTL_KGSL_GPUMEM_ALLOC_ID

Previously, the gpu address has been used to uniquely
identify each memory allocation. Upcoming patches will
introduce cases where an allocation does not always
have a gpu address, so an additional id is needed.

IOCTL_KGSL_GPUMEM_ALLOC_ID allocates pages and returns
an id.

IOCTL_KGSL_GPUMEM_FREE_ID frees an id. KGSL_SHAREDMEM_FREE
can still be used to free by GPU address, if it exists.

The id can also be passed to mmap(), shifted left by
PAGE_SIZE to get a CPU mapping for the buffer.

IOCTL_KGSL_GPUMEM_ALLOC_GET_INFO can be called to retrieve
the id and other information about the buffer.

Change-Id: I4b45f0660cb9d4a5fb1323ccc6c4aa360791c1ec
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: Support user-specified caching hints

The user allocating memory can provide hints for the caching
settings when said buffer is mapped on the user side. Try
to obey the cache settings when applicable.  The user will
be responsible for handling cache management both to and
from the GPU so add a new ioctl IOCTL_KGSL_GPUMEM_CACHE_SYNC to
support both directions (the old IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE)
only handled flushing, not invalidating. The legacy ioctl still
works it just does what it says it does - a cache flush.

Change-Id: Ic0dedbad55ce82f2b01ebc56de30d4649e2e7311
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: allow consistent CPU and GPU mappings

KGSL_GPUMEM_ALLOC_ID now takes a flag,
KGSL_MEMFLAGS_USE_CPU_MAP. When set, the GPU
mapping will be set up to match the CPU mapping
during mmap().  This feature is only supported when
using per process pagetables with the IOMMU. The
flags field of KGSL_GPUMEM_ALLOC_ID is copied back
to userspace and KGSL_MEMFLAGS_USE_CPU_MAP will
be cleared when this feature is not supported.

The IOMMU virtual address space has been adjusted
when perprocess pagetables is enabled so that the
entire userpace address range (0 to TASK_SIZE) can
have equivalent mappings on the IOMMU. For buffers
that do not have equivalent mappings, the address
range from PAGE_OFFSET to KGSL_IOMMU_GLOBAL_MEM_BASE
is used.

Change-Id: Ib61c03aa7453c3dd901c41e8fd297f66d402ae1a
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: don't fault in cached allocations

Make sure cache operations don't hit pagefaults by
backing the entire vma in mmap() instead of faulting
in pages as they're touched. Otherwise, there's a
chance that a later cache operation on the mapping
could trigger an unhandled page fault leading to
a kernel panic.

Change-Id: Ia73c8aaed2708c5b9ef46ed50fb0f5cf1ad2450c
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: Lower bounds check the number of power levels

A misconfigured board file could cause an out-of-bounds
array access through this value.

Change-Id: I64bbad0c096a2efe65376991537d810141370d72
CRs-Fixed: 439230
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
msm: kgsl: Do not dump the istore on A3XX cores

The instruction store on A3XX GPU cores isn't really an instruction store
as on A2XX and it doesn't give us any debugging value. On top of all
that it can be unstable to read in some situations. Since it is of
questionable value and questionable stability pull it from the snapshot
for all A3XX cores and move the functionality to the A2XX specific code.

Change-Id: Ic0dedbada32d8b6b9b93768d148c2624faf3ef30
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>