main.c: DDR2 to FIFO fill test works. HEAD and LASTREAD values are correct.
user_logic.v: updated connections between FIFO fsm and master registers. Used ve to read_req fifo.
hdmi_core.v: changed read_line logic to pulse ever 64 cycles in the ACTIVE region. This should ensure that the FIFO is always half full.
Need to test on board, as we don't know how long it takes for the DDR2 to actually fill up the fifo (in terms of cycles).
Merge branch 'master' of github.com:molohov/gpu2