vxlan: add implicit fdb entry for default destination

Signed-off-by: Mike Rapoport <mike.rapoport@ravellosystems.com>
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
vxlan: introduce vxlan_fdb_find_rdst

which will be reused by vxlan_fdb_delete

Signed-off-by: Mike Rapoport <mike.rapoport@ravellosystems.com>
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
vxlan: introduce vxlan_fdb_parse

which will be reused by vxlan_fdb_delete

Signed-off-by: Mike Rapoport <mike.rapoport@ravellosystems.com>
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
vxlan: allow removal of single destination from fdb entry

When the last item is deleted from the remote destinations list, the
fdb entry is destroyed.

Signed-off-by: Mike Rapoport <mike.rapoport@ravellosystems.com>
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
rtnetlink: allow using zero MAC address in rtnl_fdb_{add,del}

This is required for multiple default destinations management in VXLAN

Signed-off-by: Mike Rapoport <mike.rapoport@ravellosystems.com>
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
vxlan: fdb: allow specifying multiple destinations for zero MAC

The zero MAC entry in the fdb is used as default destination. With
multiple default destinations it is possible to use vxlan in
environments that disable multicast on the infrastructure level, e.g.
public clouds.

Signed-off-by: Mike Rapoport <mike.rapoport@ravellosystems.com>
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
drm/radeon: add a reset work handler

New asics support non-privileged IBs.  This allows us
to skip IB checking in the driver since the hardware
will check the command buffers for us.  When using
non-privileged IBs, if the CP encounters an illegal
register in the command stream, it will halt and generate
an interrupt.  The CP needs to be reset to continue.  For now
just do a full GPU reset when this happens.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add CIK chip families

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add DCE8 macro for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: adapt to PCI BAR changes on CIK

register BAR is now at PCI BAR 5.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add gpu init support for CIK (v9)

v2: tiling fixes
v3: more tiling fixes
v4: more tiling fixes
v5: additional register init
v6: rebase
v7: fix gb_addr_config for KV/KB
v8: drop wip KV bits for now, add missing config reg
v9: fix cu count on Bonaire

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: Add support for CIK GPU reset (v2)

v2: split soft reset into compute and gfx.  Still need
to make reset more fine grained, but this should be a
start.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add support for MC/VM setup on CIK (v6)

The vm callbacks are the same as the SI ones right now
(same regs and bits). We could share the SI variants, and
I may yet do that, but I figured I would add CIK specific
ones for now in case we need to change anything.

V2: add documentation, minor fixes.
V3: integrate vram offset fixes for APUs
V4: enable 2 level VM PTs
V5: index SH_MEM_* regs properly
V6: add ib_parse()

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/cik: stop page faults from hanging the system (v2)

Redirect invalid memory accesses to the default page
instead of locking up the memory controller.

v2: rebase on top of 2 level PTs

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add initial ucode loading for CIK (v5)

Currently the driver required 6 sets of ucode:
1. pfp - pre-fetch parser, part of the GFX CP
2. me - micro engine, part of the GFX CP
3. ce - constant engine, part of the GFX CP
4. rlc - interrupt, etc. controller
5. mc - memory controller (discrete cards only)
6. mec - compute engines, part of Compute CP

V2: add documentation
V3: update MC ucode
V4: rebase
V5: update mc ucode

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add support mc ucode loading on CIK (v2)

Load the GDDR5 ucode and train the links.

v2: update ucode

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: Add CP init for CIK (v7)

Sets up the GFX ring and loads ucode for GFX and Compute.

Todo:
- handle compute queue setup.

v2: add documentation
v3: integrate with latest reset changes
v4: additional init fixes
v5: scratch reg write back no longer supported on CIK
v6: properly set CP_RB0_BASE_HI
v7: rebase

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)

For gfx ring only.  Compute is still todo.

v2: add documentation
v3: update to latest reset changes, integrate emit update patch.
v4: fix count on wait_reg_mem for HDP flush
v5: use old hdp flush method for fence
v6: set valid bit for IB
v7: cleanup for release

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add ring and IB tests for CIK (v3)

v2: add documenation
v3: update the latest ib changes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: implement async vm_flush for the CP (v7)

Update the page table base address and flush the
VM TLB using the CP.

v2: update for 2 level PTs
v3: use new packet for invalidate
v4: update SH_MEM* regs when flushing the VM
v5: add pfp sync, go back to old style vm TLB invalidate
v6: fix hdp flush packet count
v7: use old style HDP flush

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>