squash extra layer of verilog
build test app when making test bit file
Fix width of burstProt and burstCache for AXI3
add option to enable use of ACP bus
Added FMC Imageon receiver interface support
added option -verilog=vdir to genxpsprojfrombsv to copy verilog files into the vivado project source directory
added support for per-bus clock inputs
remove inclusion of bitset
added gralloc/testhdmidisplay.cpp