issue solved. the problem was the latency of the readreq signal of the fifo buffer to the fifo clock signal. the design compiles, but now the sync and reset routines are corrupted again.
corrected some signal declarations
changed for loop range from 0 to noof to 1 to noof
now I have extrem distortion again, no idea why. I changed the cmv_master.vhd file and added an FSM to the buffer input process...
commented buffer read in process parts again
compiled but didnt run, just showed one image... have no reinserted the bufclear routine in the buffer readin process
still sync problems and one channel is disstorted... no idea why...
completely strange... now compiled the design without changed almost nothing, but the channels are now not disstorted and the sync procedure is better. is it possible, that the base addresses have an influence on the behaviour?
i now commented all led lines in lvds_sync. now i have the channel disstortion again... wtf
when led 5 and led 6 is changed, the design compiles and runs smoothly (without correct alignement), but there is a problem with the base address when using the nios 2 core
changed clk speeds to 100 and 10 MHz, now two channels are distorted, but syncronization is proper again
design compiles. sync routine proper. 1 channel slightly disstorted. cmv_master.vhd state from burst to readreq checked -> not necessary
changed dvi process in dvi_master.cmv... now it looks very promising. the sync seq is correct, also horizontal alignement. there are vertical stripes again... no disstortion at all. if only one frame is requested, it seems that the frame is completely correctly aligned.
no distortion at all (even when ledxS is changed), proper sync routine, very small vertical stripes... also the left most pixel should be the right most -> probably the bufreadreq signal delay in dvi_master.vhd, nios: streaming without using the while loop works correctly, while loop results in diagonal movement of the streamed frames on the monitor