OMAP: PM: move dpll2_ck lookup out of omap_pm_dsp_get_opp()

This fixes the following:

WARNING: at /usr/local/src/android/system/kernel/samsung/latona/kernel/mutex.c:198 __mutex_lock_slowpath+0x27c/0x28c()
Modules linked in: wl12xx_sdio wl12xx mac80211 cfg80211 compat
[<c00497f8>] (unwind_backtrace+0x0/0xf8) from [<c007db1c>] (warn_slowpath_common+0x4c/0x64)
[<c007db1c>] (warn_slowpath_common+0x4c/0x64) from [<c007db50>] (warn_slowpath_null+0x1c/0x24)
[<c007db50>] (warn_slowpath_null+0x1c/0x24) from [<c0573750>] (__mutex_lock_slowpath+0x27c/0x28c)
[<c0573750>] (__mutex_lock_slowpath+0x27c/0x28c) from [<c057376c>] (mutex_lock+0xc/0x24)
[<c057376c>] (mutex_lock+0xc/0x24) from [<c03e4fd8>] (clk_get_sys+0x1c/0xe0)
[<c03e4fd8>] (clk_get_sys+0x1c/0xe0) from [<c006efbc>] (omap_pm_dsp_get_opp+0x70/0xe4)
[<c006efbc>] (omap_pm_dsp_get_opp+0x70/0xe4) from [<c03cee34>] (sm_interrupt_dsp+0x7c/0x168)
[<c03cee34>] (sm_interrupt_dsp+0x7c/0x168) from [<c03caf9c>] (io_dpc+0x450/0x7a4)
[<c03caf9c>] (io_dpc+0x450/0x7a4) from [<c0083684>] (tasklet_action+0x6c/0x150)
[<c0083684>] (tasklet_action+0x6c/0x150) from [<c0084264>] (__do_softirq+0x9c/0x260)
[<c0084264>] (__do_softirq+0x9c/0x260) from [<c00844e0>] (run_ksoftirqd+0xb8/0x184)
[<c00844e0>] (run_ksoftirqd+0xb8/0x184) from [<c009bc7c>] (kthread+0x80/0x88)
[<c009bc7c>] (kthread+0x80/0x88) from [<c00455dc>] (kernel_thread_exit+0x0/0x8)
OMAP: PM: change DSP rate only when required

This should prevent the following to some extent:

WARNING: at /usr/local/src/android/system/kernel/samsung/latona/kernel/mutex.c:198 __mutex_lock_slowpath+0x27c/0x28c()
Modules linked in: wl12xx mac80211 cfg80211 compat [last unloaded: wl12xx_sdio]
[<c00497f8>] (unwind_backtrace+0x0/0xf8) from [<c007dae8>] (warn_slowpath_common+0x4c/0x64)
[<c007dae8>] (warn_slowpath_common+0x4c/0x64) from [<c007db1c>] (warn_slowpath_null+0x1c/0x24)
[<c007db1c>] (warn_slowpath_null+0x1c/0x24) from [<c0573710>] (__mutex_lock_slowpath+0x27c/0x28c)
[<c0573710>] (__mutex_lock_slowpath+0x27c/0x28c) from [<c057372c>] (mutex_lock+0xc/0x24)
[<c057372c>] (mutex_lock+0xc/0x24) from [<c005c6ec>] (omap_device_scale+0x44/0x6f0)
[<c005c6ec>] (omap_device_scale+0x44/0x6f0) from [<c03cee90>] (sm_interrupt_dsp+0x118/0x168)
[<c03cee90>] (sm_interrupt_dsp+0x118/0x168) from [<c03cb0f4>] (io_dpc+0x5e8/0x7a4)
[<c03cb0f4>] (io_dpc+0x5e8/0x7a4) from [<c0083650>] (tasklet_action+0x6c/0x150)
[<c0083650>] (tasklet_action+0x6c/0x150) from [<c0084230>] (__do_softirq+0x9c/0x260)
[<c0084230>] (__do_softirq+0x9c/0x260) from [<c00844ac>] (run_ksoftirqd+0xb8/0x184)
[<c00844ac>] (run_ksoftirqd+0xb8/0x184) from [<c009bc48>] (kthread+0x80/0x88)
[<c009bc48>] (kthread+0x80/0x88) from [<c00455dc>] (kernel_thread_exit+0x0/0x8)
board-latona-display: remove OCP interconnect constraints

L3 OPP1 is disabled, there's no need to specify constraints.
board-latona-display: code cleanup

Remove useless function, declare init_clk_disable as static and
fix code indentation.
gpu: pvr: allow to change SGX functional clock rate

Allow also to use corex2_fck as parent clock sgx_fck.
Using corex2_fck will allow to increase sgx_fck up to 266MHz.
gpu: pvr: allow to use corex2_fck as parent clock for sgx_fck
gpu: pvr: OMAP3: make ACTIVE_POWER_LATENCY a module param
gpu: pvr: define module params only when required
OMAP3: latona: clamp initial max CPU clock frequency to nominal

This prevents the system from using out-of-spec overclocking OPPs until
userspace explicitly enables them.
latona: code cleanup