arm: zynq: slcr: Swap write accessor arguments

Follow the argument order of (__raw_)write* accessors in the
xslcr_write function - hence swapping the offset and value argument.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
arm: zynq: Revise SLCR initialization

Changing the SLCR initialization in order to remove static IO mappings.
Basic SLCR inititalization is done in timer init.
Providing the io-remap area for the SLCR early during boot, as required
for clock init. Furthermore, clock_init is called from the slcr init routine,
passing the slcr_base address as parameter.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: Move clk.h out of mach headers

The patch is the part of moving to MULTIPLATFORM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: Do not define SCU physical address

Autodetect scu base address through Cortex A9 registers.
smp_alloc use 1:1 virt:phys mapping.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: Remove slcr ioremap from platsmp

Do not map slcr again which is already mapped.
The next step is to remove xslcr_write from this driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: slcr: Provide base address through global pointer

Suspend code which is executed out of OCM while DRAM is in self-refresh
mode must be self-contained. Therefore it cannot use the xslcr
accessor functions and requires a pointer to the remapped memory.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clk: zynq: Clear PLL bypass qual bit

In order to being able to bypass the PLL the bypass qual bit
in the PLL control register must be cleared. This patch adds
clearing the bit during clock registration.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clk: zynq: pll: Rename struct members

Sync struct member names for the PLL struct with mainline:
Rename pll(ctrl|cfg|status) to pll_(ctrl|cfg|status).

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clk: zynq: pll: Don't allocate spinlock separately

Change the type of the lock in the PLL struct from 'spinlock_t *'
to spinlock_t, saving an additional call to kmalloc.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
cpufreq: zynq: Select PM_OPP

Zynq's cpufreq driver relies on the OPP library. Automatically
add it to the kernel when the cpufreq driver is added to ensure a
working setup.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
memory: Add driver for Zynq SMC

This adds a driver for Zynq's static memory controller.
The SMC (compatible with ARM's PL353)  supports NAND, NOR and SRAM memory.
This driver separates SMC generic code from the memory specific drivers
and provides an API for them.
Additionaly, the SMC driver manages power management features like
clock gating.

This patch also has impact on the device tree bindings. Existing NAND and NOR
nodes have to converted to subnodes of the new SMC node.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xilinx: dts: Update zedboard dts

Generated by the latest device-tree BSP with one exception
which is manually adding flash node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
clk: zynq: Convert PLLs to DT driven init

Initialize the PLLs from DT driven data and get rid of the obsolete
init code in zynq/clk.c.
Also, adding documentation for the DT binding.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: memory: Enable memory drivers for zynq by default

Select MEMORY by default and add dependency on smc in nand driver.

This should be the part of patch:
"memory: Add driver for Zynq SMC"
(sha1: 6cffa68066c3dbace05b6937b8e3d671ca6cd62a)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
microblaze: Remove unused sp605_le.dts

All dtses should be generated by device-tree bsp.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
pmod: Clean compilation and sparse warnings

This is only one simple step do no produce compilation
warnings and sparse warning which are always bad sign
of driver code quality.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
asm-generic: io: Fix ioread16/32be and iowrite16/32be

Fix ioreadXXbe and iowriteXXbe functions which did
additional little endian conversion on native big endian systems.
Using be_to_cpu (cpu_to_be) conversions with __raw_read/write
functions have resolved it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Will Deacon <will.deacon@arm.com>
CC: linux-arch@vger.kernel.org
tty: serial: uartlite: Fix sparse and checkpatch warnings

Clean coding style and sparse warnings.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
tty: serial: uartlite: Support uartlite on big and little endian systems

Use big and little endian accessors function to reflect system configuration.
Detection is done via control register in ulite_request_port.

Tested on Microblaze LE, BE, PPC440 and Arm zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
xilinx: Documentation/devicetree - add description for "port-number" property

This property is used by xsysace device (drivers/block/xsysace.c).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>