R600: Use function inputs to represent data stored in gpr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
Print new JavaScript calling conventions symbolically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194427 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the recently added anyregcc convention to handle spilled operands.

Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!"

The primary purpose of anyregcc is to prevent a patchpoint's call
arguments and return value from being spilled. They must be available
in a register, although the calling convention does not pin the
register. It's up to the front end to avoid using this convention for
calls with more arguments than allocatable registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194428 91177308-0d34-0410-b5e6-96231b3b80d8
Lower X86::MORESTACK_RET and X86::MORESTACK_RET_RESTORE_R10 in
X86AsmPrinter::EmitInstruction, rather than X86MCInstLower::Lower.

The aim is to improve the reusability of the X86MCInstLower class by making it
more function-like. The X86::MORESTACK_RET_RESTORE_R10 pseudo broke the
function model by emitting an extra instruction to the MCStreamer attached to
the AsmPrinter.

The patch should have no impact on generated code. 
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194431 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add test that fails due to requiring i64 mul for pointers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194433 91177308-0d34-0410-b5e6-96231b3b80d8
Extract a bc attr parsing helper that returns Attribute::None on error

The parsing method still returns llvm::error_code for consistency with
other parsing methods.  Minor cleanup, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194437 91177308-0d34-0410-b5e6-96231b3b80d8
Change the default branch instruction to be the 16 bit variety for mips16.
This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Change formatting of printed registers.

Print the range of registers used with a single letter prefix.
This better matches what the shader compiler produces and
is overall less obnoxious than concatenating all of the
subregister names together.

Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1,
it will print s[0:1] and so on.

There doesn't appear to be a straightforward way
to get the actual register info in the InstPrinter,
so this parses the generated name to print with the
new syntax.

The required test changes are pretty nasty, and register
matching regexes are now worse. Since there isn't a way to
add to a variable in FileCheck, some of the tests now don't
check the exact number of registers used, but I don't think that
will be a real problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
Added basic unit test for llvm-cov.

This test compares the output of llvm-cov against a coverage file
generated by gcov. Since the source file must be in the current
directory when reading GCNO files, the test will first cd into the
Inputs directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194451 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-cov: Added call to update run/program counts.

Also updated test files that were generated from this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194453 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Added basic unit test for llvm-cov."

This reverts commit r194451.

Not sure why the tests are failing on the buildbot. They run fine on my
local machine. Could it possibly be because of the endianness of the
architectures? The GCNO and GCDA files are little-endian encoded, and
llvm-cov expects it to remain that way. Is this a safe assumption?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194454 91177308-0d34-0410-b5e6-96231b3b80d8
Add new FileCheck feature to 3.4 release notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194456 91177308-0d34-0410-b5e6-96231b3b80d8
Correct a glitch in r194424 which may invalidate iterator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194457 91177308-0d34-0410-b5e6-96231b3b80d8
Change data structure to memorize computed result in ScalarEvolution

Replace std::map with SmallVector to memorize the cached result since SCEV usually belongs to little Loop/BB
Linear scan on SmallVector is faster than std::map.

Code reviewer : Andrew Trick.
Test result   : Pass Unit Test & LLVM Test Suite

401.bzip2	0.425721	0.419981	101.37%
403.gcc		24.53855	24.2667		101.12%
429.mcf		0.060847	0.059944	101.51%
433.milc	0.646009	0.636119	101.55%
444.namd	1.383928	1.370614	100.97%
445.gobmk	5.836575	5.800225	100.63%
450.soplex	1.911257	1.895963	100.81%
456.hmmer	1.039565	1.032534	100.68%
458.sjeng	0.897401	0.885567	101.34%
464.h264ref	3.645908	3.577991	101.90%
470.lbm		0.049456	0.048398	102.19%
471.omnetpp	5.638575	5.60435		100.61%
bitmnp01	0.045738	0.045291	100.99%
cjpegv2data	0.304359	0.302833	100.50%
idctrn01	0.046433	0.045763	101.46%
quake2		4.534416	4.4952		100.87%
quake		2.688566	2.659208	101.10%
xcsoar		12.42545	12.30385	100.99%
linpack		0.038739	0.03803		101.86%
matrix01	0.053564	0.0528		101.45%
nbench		0.402867	0.395803	101.78%
tblook01	0.021265	0.021015	101.19%
ttsprk01	0.066384	0.065566	101.25%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194459 91177308-0d34-0410-b5e6-96231b3b80d8
XCore target: return error for unsupported alignment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194463 91177308-0d34-0410-b5e6-96231b3b80d8
Add XCore support for ATOMIC_FENCE.

ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There
is no need to emit an instructions since the XCore provides sequential
consistency.

Original patch by Richard Osborne

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194464 91177308-0d34-0410-b5e6-96231b3b80d8
XCore target test for hidden declaration

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194465 91177308-0d34-0410-b5e6-96231b3b80d8
XCore target: fix bug in aligning 'byval i8*' on the stack

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194466 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Change constant used in ori tests to avoid conflict with bseti (also xori to avoid bnegi)

Upcoming commit(s) are going to add support for bseti and bnegi. This would
cause some existing tests to (correctly) change behaviour and emit a different
instruction. This patch prevents this by changing the constant used in ori and
xori tests so that they will not be matchable by the bseti and bnegi patterns
when these instructions are matchable from normal IR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8