Minor VHDL bug fixes
hdl/primitives/ocpi/types_body.vhd: more convenient conversion functions for ulonglong types
hdl/primitives/ocpi/types_pkg.vhd: ditto
tools/cdk/include/hdl/modelsim.mk: compile verilog before vhdl when mixed
-- not perfect, but better than the other way
tools/cdk/ocpigen/ocpigen/src/wip_HDL.cxx: wierd one-worker boundary condition type/bug