README: fix quick intro
Add setup.py
xilinx_ise: implement NoRetiming synthesis constraint
xilinx_ise: enable register balancing
mibuild: Add platform for Xilinx ML605 board
platforms: add KC705
crg: support for resetless system clock domain
platforms/papilio_pro: no reset signal by default
platforms/m1: add pots pins
platforms/papilio_pro: swap tx/rx to be consistent with M1
Require Python 3.3
Use migen.fhdl.std
platform/rhino: rename ismm data out signal to locked
xilinx_ise: improve parameter passing
kc705: add ce_n for flash
Merge branch 'master' of https://github.com/milkymist/mibuild