risugen: allow shift by 4 in reg_plus_reg_shifted

aarch64 SIMD/fp instruction variants require addressing
in the form register plus register shifted by 4, to align
128bit data.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: implement more SIMD/fp insns and variants

add SIMD/fp LDR/STR unsigned imm offset,
add SIMD/fp LDR/STR register offset (only LSL option),
align some previous loads and stores optimally.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>