ARM: OMAP4: PM: Avoid expensive cpu_suspend() path for all CPU power states except off

Current CPU PM code code make use of common cpu_suspend() path for all the
CPU power states which is not optimal. In fact cpu_suspend() path is needed
only when we put CPU power domain to off state where the CPU context is lost.

Update the code accordingly so that the expensive cpu_suspend() path
can be avoided for the shallow CPU power states like CPU PD INA/CSWR.

The patch has been tested on OMAP4430 and OMAP5430(with few out of tree patches)
devices for suspend and CPUidle.

Cc: Kevin Hilman <khilman@deeprootsystems.com>

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
ARM: OMAP4+: PM: Consolidate MPU subsystem PM code for re-use

OMAP5 and future OMAP based SOCs has backward compatible MPUSS
IP block with OMAP4. It's programming model is mostly similar.
Hence consolidate the OMAP MPUSS code so that it can be re-used
on OMAP5 and future SOCs.

No functional change.

Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
ARM: OMAP4+: Make secondary_startup function name more consistent

Current code has rather inconsistent function names for 'secondary_startup'
routines. Update it to make it more consistent.

Suggested by Kevin Hilman as part of OMAP5 PM patch review.

Cc: Kevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5

OMAP5 has backward compatible PRCM block and it's programming
model is mostly similar to OMAP4. Same is going to be maintained
for future OMAP4 based SOCs. Hence consolidate the OMAP4 power
management code so that it can be re-used on OMAP5 and later devices.

While at it, update the kernel-doc for omap4_pm_init().

Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
ARM: msm: Remove init_irq declaration in machine description

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for msm as well.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: David Brown <davidb@codeaurora.org>
Merge tag 'omap-pm-v3.10/cleanup/pm' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-v3.11/pm

OMAP PM cleanups for v3.10
ARM: OMAP2+: control: add OMAP5 support for dsp boot programming

Support for OMAP5 is added to the omap_dsp_ctrl_write_boot_addr()
to enable the DSP boot.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: nand: reorganize gpmc timing values

This patch removes omap2_nand_gpmc_retime() which was used to quirk
some timing values before gpmc_cs_set_timings(). Due to recent changes,
gpmc_cs_set_timings() has evolved so that there is no more need for a
retime function.

To keep the gpmc configuration consistent for legacy board files, this
patch also adds oe_on and we_on to nand_default_timings[] as they
would be by the retime function.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: Allow NAND transfer mode to be specified in DT

OMAP devices support various NAND transfer modes.

Currently all device-tree definitions will use the default "prefetch
polled" mode, so this patch enables the transfer mode to be specified
in the device-tree.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: dts: OMAP2+: Simplify NAND support

Commit 8c8a777 (ARM: OMAP2+: Add function to read GPMC settings from
device-tree) added a device-tree property "gpmc,device-nand" to indicate
is the GPMC child device is NAND. This commit should have updated the
GPMC NAND documentation (Documentation/devicetree/bindings/mtd/gpmc-nand.txt)
to list the property "gpmc,device-nand" as a required property and also
updated the example. However, this property is redundant and not needed
because the GPMC child device node for NAND is called "nand". Therefore,
remove this property.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: bcm2835: Add Raspberry Pi's ACT LED to DT

The Raspberry Pi board has one GPIO-controlled LED labeled "ACT". Add it
to the DT via the gpio-leds driver, so users can control it from
userspace. If CONFIG_LEDS_TRIGGER_HEARTBEAT is set, the LED will also
signal some sign of life.

The GPIO circuitry is low-active. And as the bootloader may decide to
switch the LED on at boot time, the default state is 'keep'.

Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
ARM: tegra: finalize USB EHCI and PHY bindings

The existing Tegra USB bindings have a few issues:

1) Many properties are documented as being part of the EHCI controller
node, yet they apply more to the PHY device. They should be moved.

2) Some registers in PHY1 are shared with PHY3, and hence PHY3 needs a
reg entry to point at PHY1's register space. We can't assume the PHY1
driver is present, so the PHY3 driver will directly access those
registers.

3) The list of clocks required by the PHY was missing some required
entries.

4) UTMI PHY Timing parameters are added

5) VBUS control is now specified using a regulator rather than a plain GPIO

6) Added nvidia,is-wired property to indicate whether the device is
hard wired on the board, or pluggable.

This patch fixes the binding definition to resolve these issues.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: modify ULPI reset GPIO properties

1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active
low nature of the GPIO.
2. Placed USB PHY DT node immediately below the EHCI controller DT nodes
and corrected reg value in the name of USB PHY DT node.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: update device trees for USB binding rework

This patch updates all Tegra board files so that they contain all the
properties required by the updated USB DT binding. Note that this patch
only adds the new properties and does not yet remove the old properties,
in order to maintain bisectability. The old properties will be removed
once the driver has been updated to assume the new bindings.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
[swarren: fixed some newly added regulator-name properties to better
match schematic, avoided duplicate regulator-name on Whistler.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: emc: correction of ram-code parsing from dt

Change tegra_emc_ramcode_devnode() to get ram-code from child node instead of
parent.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add an assembly marco to check Tegra SoC ID

There are some Tegra SoC ID checking code around the low level assembly
code. Adding a marco to replace them. For the single image to support all
the Tegra series, we may also need the marco in other common code. So we
make it become a marco for the usage.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9

For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: make tegra_resume can work for Tegra114

Tegra114 had a newer flow controller hardware that makes its behavior and
configurations are different with other Tegra series. We fix the common
resume function of tegra_resume to make it can work on Tegra114 by checking
SoC ID. And also checking CPU primary part number to isolate the support
code for Cortex A9 and A15.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra114: add power up sequence for warm boot CPU

For Tegra114, once the CPUs were powered up by PMC in cold boot flow. The
flow controller will maintain the power state and control power sequence
for each CPU by setting event trigger (e.g. CPU hotplug ,idle and
suspend power down/up).

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops

The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>