Made a bit more room between CLOCKGEN_OEB# and FE_I2C_SDA, to address DRC (due to rounding error?) in KiCAD -testing.
Corrected design rules to match newer layer stack: minimum trace of 6.5mil, minimum clearance, 5.0mil.
Altered 50 Ohm traces to new layer stack widths.
Fixed up some non-50 Ohm traces that needed widening due to new trace minimum widths.
Changed date on silkscreen.