dma: support uncontrolled streaming between two slaves
move platform specific modules into conditional folders
spi_flash: memory-mapped flash memory (can program an Altera FPGA)
serial_lcd + spi_flash: missing copyrights
spi_flash: add enough parameters to work around buggy altera spi timings
altera: add flash interface
remove gc_wfifo in favour of generic_async_fifo
altera pcie: fix a race condition in the bar switchover

On slow Wishbone slave devices (eg. flash), the next request might
be decoded by the PHY before first has exited the read_first state.
In this case, the bar could change causing the mux to prematurely
lower the stall line.
xwb_streamer: reduce to a wrapper of xwb_dma

The optimizer should be able to remove all the control registers
as they are unchanging, so nothing is lost.
xwb_dma: convert variables into signals

We cannot access variables outside the process, which we will need
to be able to do in the next patch.
xwb_dma: convert custom array to generic_simple_dpram

Use the generics for memory insted of infererence.
Also, remove read-during-write bypass by tweaking index comparisons.
altera dpram: quell modelsim warning
altera dcfifo: synchronize read reset
onewire: fix synthesis warnings
altera pcie: use assigned vendor/device ID
Merge remote-tracking branch 'upstream/master'