A few XML simplifications/shortcuts, and an adapter reset signal bug fix.

components/bias.rcc/bias.c: make code a little smaller
components/bias.rcc/bias.xml: use new "spec" attribute as a convenience vs. xi_include
tools/ocpigen/include/wip.h: support "port" as a synonynm for "datainterfacespec"
tools/ocpigen/src/parse.cxx: ditto, plus "protocol" attribute on port
tools/ocpigen/src/hdl-assembly.cxx: fix bug for reset signal into adapters in verilog assys