added extra error handling to the code.
Also made the "timeout" of DMA an emergency message (that way my logic analyzer can trigger on serial activity plus a bit of data kept pre-flight, that might be of interrest)

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
running version - refactored somehow to make the "race-condition" go away...

Actually the "race condition" are 2 things:
* 2d DMA are not 100% guaranteed to be in the correct sequence all the time
  so it is better to use multiple transfers to configure 2 Registers in the correct order...
* Sometimes SPI TX/RX resets are not happening when we do them - they take a few cycles
  so I had to separate the LEN/CS+RESET setting from a single 2D transfer
  to 3 DMA transfers - CS Set+TX/RX, Length set, and final CS Set (without Reset bits)

Then it actually works as expected...

Tests have shown that for over 5000 seconds this issue does not show up any longer.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>