(HLS) correct some mistakes + remove untagged write + remove ransfer
loop (just mvseq and mvrecon to debug)
(HLS) remove useless buffers
(HLS) model compatible with dataflow directive (but not better perfs!)
(Backends) Adding naive modulo support on DivisionSubstitution
Merge branch 'master' of https://github.com/orcc/orcc.git
(Backends) Now DivisionSubstitution visits the action scheduler too
(HLS) Top compatible with vivado dataflow directive
(HLS) back to stable version with correct hardware simulation
(TTA) Fix TCL script used to launch RTL simulation.
(TTA) Add generation of dual port RAM using coregen to the Xilinx flow.
(TTA) Fix small error in vector length.
(frontend) Enable building IR only for needed files

Simply specify a network qualified name in second argument of net.sf.orcc.cal.cli application
Merge branch 'master' of github.com:orcc/orcc
(frontendcli) Prevent exception when running orcc
(frontendCli) Fix a NullPointerException when running with Network
parameter
(TTA) Lets LLVM removing unconnected input port.
(LLVM) Notices unconnected port.
(frontend) Fix bug in recursive calls
(Simulator) Forbids execution of actions accessing unconnected ports.
Merge branch 'master' into instanciation

Conflicts:
	eclipse/plugins/net.sf.orcc.backends/runtime/TTA/orcc_/design.py
	eclipse/plugins/net.sf.orcc.backends/src/net/sf/orcc/backends/c/hls/InstancePrinter.xtend