radeonsi: respect semantic indices for COLOR[i] fragment shader outputs

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: add the vertex shader position output if it's missing

This fixes a lockup in piglit/spec/glsl-1.40/execution/tf-no-position.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
winsys/radeon: add the implementation of fences from r300g
r600g,radeonsi: use fences provided by the winsys
i965: s/Muchnik/Muchnick/.

Reviewed-by: Eric Anholt <eric@anholt.net>
i965/fs: Match commutative expressions with reversed arguments.

total instructions in shared programs: 1645011 -> 1644938 (-0.00%)
instructions in affected programs:     17543 -> 17470 (-0.42%)

Reviewed-by: Eric Anholt <eric@anholt.net>
glsl: Optimize (not A) or (not B) into not (A and B).

A few Serious Sam 3 shaders affected:

instructions in affected programs:     4384 -> 4344 (-0.91%)

Reviewed-by: Eric Anholt <eric@anholt.net>
glsl: Optimize (not A) and (not B) into not (A or B).

No shader-db changes, but seems like a good idea.

Reviewed-by: Eric Anholt <eric@anholt.net>
glx: Fix return value from indirect_bind_context

_XReply returns 1 on success, but indirect_bind_context returns 0 on
success.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70486
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
gallium: add PIPE_CAP_MIXED_FRAMEBUFFER_SIZES

This CAP will determine whether ARB_framebuffer_object can be enabled.
The nv30 driver does not allow mixing swizzled and linear zsbuf/cbuf
textures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
mesa/st: disable ARB_framebuffer_object when no driver support.

When PIPE_CAP_MIXED_FRAMEBUFFER_SIZES is not provided, parts of
ARB_framebuffer_object can't be supported, such as on NV30.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
i965: Try not to reverse-schedule things when doing LIFO scheduling.

The LIFO plan was simple: Take the most recently made available
instructions, and pick those first.

But because of the order we were pushing things onto our list of
available-to-schedule instructions, it meant that when a set of
instructions was made available at the same time (for example, everything
at the start of the program that didn't depend on other instructions) we'd
schedule them in reverse order.

If you had 10 texture calls in a row in your program, each with
independent argument setup, we'd set up the last texture call's args and
execute it first, even though we wouldn't be able to consume its results
until we'd finished the other 9 texture calls (assuming consumption of
texture results happens near each texture call, and combines it with
another texture result, which is normal for a convolution shader).

To fix this, walk the list for doing LIFO in the order that instructions
were originally generated in the program, but choose to push
newly-made-available instructions to the other end of the list instead.

total instructions in shared programs: 1587242 -> 1586290 (-0.06%)
instructions in affected programs:     7801 -> 6849 (-12.20%)
GAINED:                                76
LOST:                                  67

Thanks to Chia-I Wu for pointing out the bug in my first version of the
patch that made it a huge loss.

Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/fs: Stop trying to hack around MRF dep chains on gen7+ LIFO scheduling.

This was a hack to avoid choosing to schedule all texturing before
consumption of any texture results due to the way dependency chains worked
out in the presence of MRFs.  On gen7, we don't have MRFs, so the problem
doesn't apply, and this was just badly constraining our scheduling.

total instructions in shared programs: 1615306 -> 1612534 (-0.17%)
instructions in affected programs:     9958 -> 7186 (-27.84%)
GAINED:                                259
LOST:                                  9

Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Weaken the flushing in gen7_end_transform_feedback().

Since 062317d6671 (i965: Go back to using the kernel SOL reset feature.)
we've been flushing the batch on BeginTransformFeedback().  So it's not
necessary to do it on EndTransformFeedback().  A PIPE_CONTROL will work.

This makes gen7_end_transform_feedback() exactly the same as the gen6
variant.  However, they'll diverge again shortly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
glsl: Add ARB_gpu_shader5 textureGatherOffset signatures

- gsampler2DRect
- optional `comp` parameter

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: relax const offset requirement for textureGatherOffset

Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be
a constant expression.

With that extension, it is relaxed to be an arbitrary expression.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: add missing tg4 case in brw_instruction_name

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets.

The generator code ends up clearer this way than if we had to sniff
via the message length. Implemented via the gather4_po message in
hardware, which is present in Gen7 and later.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: relax brw_texture_offset assert

Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965/fs: add support for gather4 with nonconstant offsets

V3: fixup crazy check for whether we need to emit the coordinate after
    custom handling.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>