coding.py: rewrite If() to make verilog more readable
support re-slicing and non-unit step size

* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
genlib/misc: remove bitreverse
fhdl/tools: separate complex slice lowerer from basic lowerer
fhdl/verilog: lower complex slices before reset insertion
examples/complex: do not use variable
merge
cleanup