Generate ps7_sdio clock-frequency again

Here is confusion in device-tree which is that sometimes
clock-frequency is output freq instead of input freq.
For sdhci is this property required by shdci-pltfm.c:
sdhci_get_of_property and there is no way how to
pass this clock frequency directly from the driver
because structure is not initialized in driver code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq:SMC: Add "xlnx,ps7-smc" to ps7_smcc compatible string

This is required to match the kernel smc driver.

Signed-off-by: Jason Wu <huanyu@xilinx.com>
Setup main_memory_bank if is not defined in mld

Device-tree MLD do not define main_memory_bank variable
that's why ram at xps_mch_emc can't be generated
and BSP reports "No memory nodes found".
Setup the zero bank as default value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add update tree child node update feature

tree_node_update function is created to allow user to update particular
child node of a tree.

Signed-off-by: Jason Wu <huanyu@xilinx.com>
Zynq: Nand: Set NAND transactions address range to 16MB

Currently tools provide 0x1000 reg size which will cause kernel
oops because the nand driver will access the address beyond 0x1000 range.

Signed-off-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq: NOR: Rename the primary flash node to flash

Rename the NOR flash node name from "ps7-nor" to "flash".

Signed-off-by: Jason Wu <huanyu@xilinx.com>
zynq: Generate ocm memory node

OCM is automatically set by u-boot to high possition.
SDK provide low baseaddress which is 0 and that's why
it is rewritten.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: ddrc: Add ps7-ddrc compatible property

All zynq IPs provide 1.00.a version which is
pretty long and useless. Use shorter version.

Generated node:
ps7_ddrc_0: ps7-ddrc@f8006000 {
	compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc";
	reg = < 0xf8006000 0x1000 >;
	xlnx,has-ecc = <0x0>;
} ;

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb2_device: Add backward compatible property

Add backward compatible property for PLB and AXK
usb2_device IPs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Revert "BSP: device-tree: Do not generate mdio node for ethernet lite."

This reverts commit 44ac57080da215757985361b902dfded413f234d.

We should generate that mdio bus correctly. Without it
is causing problems on some systems.

Reported-by: Subbaraya Sundeep Bhatta <subbaraya.sundeep.bhatta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All zynq platforms should use bus name amba instead of axi

The main reason is mainline pl330 driver which requires
amba probing which is done on amba bus.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add enet/DMA control-stream

The AXI Ethernet and DMA have not one but two AXI Stream connections between
them. To make the dtb more accurate both these linkages should be in the dts
independently.

This initial patch is about getting the syntax right in the normal use case,
where both streams run in parallel from a single Ethernet to a single DMA.
But what we really need to do long term is check the control and data stream
independently and potentially even connect them to different devices.

My motivation here is QEMU. QEMU now has support for multiple stream connections
to the one device and the FDT driven machine model instantiation wants this.
Othewise we need specific "if AXI DMA ... " logic to tell QEMU to interpret the
axistream-connected phandle linkage as not one but two streams.

Should be zero kernel side impact as is a purely additive dts change.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Add support for amba pl330

Add proper pl330 mainline description.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add support for axi_tft IP core

Generate proper compatible string for tft IP
and also generate xlnx,dcr-splb-slave-if = 0x1 which
is required by Linux driver which was designed for PPC.
Generating interrupt is also added for this core.

Generated node:
axi_tft_0: tft@7a000000 {
	compatible = "xlnx,axi-tft-1.00.a", "xlnx,xps-tft-1.00.a";
	interrupt-parent = <&microblaze_0_intc>;
	interrupts = < 0 0 >;
	reg = < 0x7a000000 0x10000 >;
	xlnx,dcr-splb-slave-if = <1>;
	xlnx,default-tft-base-addr = <0xa5000000>;
	xlnx,family = "virtex6";
	xlnx,i2c-slave-addr = <0x76>;
	xlnx,max-burst-len = <0x10>;
	xlnx,tft-interface = <0x1>;
} ;

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
ps7_ethernet: Add phy-mode property

This adds the phy interface type entry to emacps device-tree node
based on C_ETH_MODE configuration parameter.
C_ETH_MODE - '1' (MIO -> i/f will be RGMII)
C_ETH_MODE - '0' (EMIO -> i/f will be GMII)

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
phy: Move default phy options to gen_mdiotree

Move it there to enable option to call gen_phytree directly
with different phy setting.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
emacps: Add support for gmii2rgmii convertor in PL

If gmii2rgmii convertor is present in the system
it lies on mdio bus with specific phy address.
And phy node for this convertor is generated there.

Dts fragment:
ps7_ethernet_1: ps7-ethernet@e000c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "xlnx,ps7-ethernet-1.00.a";
	gmii2rgmii-phy-handle = <&phy1>;
	interrupt-parent = <&ps7_scugic_0>;
	interrupts = < 0 45 1 >;
	local-mac-address = [ 00 0a 35 00 00 00 ];
	phy-handle = <&phy0>;
	phy-mode = "gmii";
	reg = < 0xe000c000 0x1000 >;
	xlnx,enet-clk-freq-hz = <0x7735940>;
	xlnx,enet-reset = <0xffffffff>;
	xlnx,enet-slcr-1000mbps-div0 = <0x1>;
	xlnx,enet-slcr-1000mbps-div1 = <0x1>;
	xlnx,enet-slcr-100mbps-div0 = <0x1>;
	xlnx,enet-slcr-100mbps-div1 = <0x5>;
	xlnx,enet-slcr-10mbps-div0 = <0x1>;
	xlnx,enet-slcr-10mbps-div1 = <0x32>;
	xlnx,eth-mode = <0x0>;
	xlnx,has-mdio = <0x1>;
	xlnx,ptp-enet-clock = <111111115>;
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: phy@7 {
			compatible = "marvell,88e1116r";
			device_type = "ethernet-phy";
			reg = <7>;
		} ;
		phy1: phy@8 {
			compatible = "xlnx,gmii2rgmii";
			device_type = "ethernet-phy";
			reg = <8>;
		} ;
	} ;
} ;

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>