ARM sched model: Add SIMD/VFP load/store instructions on Swift

Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.
CodeGenSchedule: Use resize instead of copying a vector
Perform dynamic alignment computations so that the data in TypeLocs is
correctly aligned.  Not performing such computations led to misaligned loads,
which crash on some platforms and are generally bad on other platforms.

The implementation of TypeLocBuilder::pushImpl is rather messy; code using
TypeLocBuilder accidentally assumes that partial TypeLocs are
laid out like a complete TypeLoc.  As a followup, I intend to work on
fixing the TypeLocBuilder API to avoid exposing partial TypeLocs; this should
substantially simplify the implemementation.

Fixes PR16144.
Diagnose malformed x86 inline asm using 'y' constraint.

X86's 'y' inline assembly constraint represents an MMX register, this change
prevents Clang from hitting an assertion when passed an incompatible type to
deal with.