pull in VHDL files for driving a test bench from data files.
update memory map information: boot rom location etc.
import ophis 6502 assembler
add python script for generating VHDL ROM/RAMs from binary file.
tie in with 6502 assembler to allow generating VHDL ROM/RAMs direct
from 6502 assembly code.
fix vhdl syntax error in generated files.
update dependencies so that rom vhdl files get rebuilt when
required.
add kernel65.vhdl to project.
created fastio interface (as yet un driven).
added rom template for makerom script.
allow operands to be read/written from fast io.
cause fast io to be mapped to upper 16MB of address space.
fix RMW instructions. They can now work on IO addresses.
update power-on memory map
fix bug that broke fastio mapping.
split ram bank registers into read/write/instruction fetch sets.
update power on memory map to map kernel65 rom as read only.
add missing irq and nmi to cpu sensitivity list.
update memory map to reflect reality.
update cycle counts to reflect that memory write pipelining has
been implemented.
implement execute instructions from fast IO.  Will result in several
cycle penalties as we always take 3 cycles to fetch the instruction
and operands instead of just one as with fast ram.
document 2 cycle penalty for instructions executing in I/O memory.
update simple test bench to hold a container of cpu, rather than
bare cpu.
remove unneeded test bench components.
fix synthesis issues with ISE.
Work towards being able to simulate.