This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the extra leading 0 from VMAXNMND.
The N3VDIntnp pattern takes bits<5> and I gave it 6 bits.

Thanks to Jiangning Liu for spotting it!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186568 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Rename and formatting fixes

In hindsight, using "RISBG" for something that can be any type of
R.SBG instruction was a bit confusing, so this renames it to RxSBG.
That might not be the best choice either, since there is an instruction
called RXSBG, but hopefully the lower-case letter stands out enough.

While there I fixed a couple of GNUisms that had crept in --
sorry about that!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186569 91177308-0d34-0410-b5e6-96231b3b80d8