generic_dpram: Should be read-first, as documented.

Newer quartus versions recognized that the code describes write-first logic,
which requires combinatorial bypass logic. Unfortunately, this is also impossible
with two clocks. Thus they reject synthesis. This manifests as the WR endpoint
RX path failing to synthesize.
wb_slave_adapter: rewrote using definition from the B.4 standard.

The old version didn't do WE properly and was rather strangely coded.
altera/generic_dpram: Support Arria5

Unfortunately, Arria5 cannot do read-old-data for the same port.
This formulation describes a dual-ported RAM with:
  write-first/read-new-data for RW conflict on same port
  read-first /read-old-data for RW conflict between ports
... which is exactly what Arria5 supports (and Arria2 can do too).

Users of the generic_dpram should simply avoid simultaneous
RW on the same port, as the result is undefined (Altera != Xilinx).
Merge remote-tracking branch 'upstream/master'