Tiny optimization for complier templates for arm.

1. Remove possible bubble in TEMPLATE_STRING_INDEXOF.S
2. Remove 1 instruction and reorder the opcodes
   TEMPLATE_MUL_LONG.S
3. Reorder ldr r2 instruction in TEMPLATE_RETURN.S

Change-Id: I571c1278aa72cb1e6dbc6efe433932d5e9591b80
Fix a leak in Dalvik_dalvik_system_DexFile_openDexFile

Change-Id: I2b394c620af31914606763b35847b7f412774cf4
Fix a minor leaks caused by failed initializations.(typo)

Change-Id: I62bc3ea48938a4f54e9f47218d4025e954a6d566
Fix a minor leak in handleVM_CreateString

Change-Id: I3273e5d2eb4621202837c43270a466fe056d6894
Optimize dvmHash Loops.

pHashTable->tableSize is working as volatile variable & is evaluated on every iteration.
Help compiler to define tableSize as local(Register) variable.

Change-Id: Iecdea3ecb810319d461ff3924ef21fd6c2d69d1e
Optimize opcodes to avoid bubble in pipeline.

Possible bubbles between fetch(ldr) and extract(and)
Excute subsequent instruction(s) inbetween the bubble by reordering instruction.

Change-Id: I76d89ed6bc4ca44673231375cc529fdbfd5a8030
Remove possilbe leaks in dalvik.

Add missing free() calls.

Change-Id: Id602b84ba8f15fef1851f37e3d5aac214ac67de1
Possible leak in dvmAllocRegion

In error case mmapped ptr 'base' is not munmapped.

Change-Id: I9e43841371fee6b7c092fe9a8922ae82e78805ed
Reclaiming attribute obj after pthread_create

call pthread_attr_destroy in order to reclaim attribute object.

Change-Id: I2592903ef67101a7c656a3ab0ad243a9716298b5
dalvik: squashed JIT improvements

JIT: Performance fix for const doubles

Some recent Arm processors take a performance hit when
creating a floating point double by loading it as a pair of singles.
Legacy code to support soft floating point doubles as a pair of core
registers loaded double immediates in this way.

With the CL, we handle double immediates as a single unit.

(cherry-pick of c8129911e598ad0ca8d7b31012444ab6ce8bce45.)

Change-Id: Ic1512e34bfd233a6f5ffd58ce843965adbbad875

Fix JIT bug related to immediate doubles

Change 256211 (JIT: Performance Fix for const doubles) introduced a
defect that can cause the JIT to use the wrong floating point
double constant in traces in which the following conditions hold:

   o Two (or more) different 64-bit floating point constants are used.
   o The physical register holding the first constant is still live
     at the time the second constant is used.
   o The low 32 bits of the two constants are identical.

In this situation, the load/copy optimization pass will incorrectly
determine that the two constants are the same, delete the load of
the second constant and re-use the first constant value.

Note: this problem only occurs with 64-bit floating point literals.
64-bit long literals are unaffected.

This CL works around the problem, and a subsequent CL will rework
disambiguation of 64-bit immediates in a somewhat cleaner fashion.

(cherry-pick of c1757a6deab0ca0bfd42c38612d92b2f26c41dbe.)

Change-Id: I795b4b753550d2745cbbdd83ae25f4a7088990f6

Fix JIT initialization race

See b/8767735 Slow thread in thread spin test

A race exists in thread creation/JIT initialization that can
leave the JIT permanantly disabled for a thread (typically
the first interpreter thread).

(cherry-pick of 67985d960f5c877f86d0bba251d2d55c7a062b8d.)

Change-Id: Ic7e3a1cde2833ac78455fa5d465156b5e0896fc1
Fix some leaks in VfyBasicBlock & BitVector.

Change-Id: I20050135588fc96268911b8ab690b04c8ad949bc
JIT: Hoist loop load operations above loop.

Hoists Dalvik frame load operations outside of loops, when possible.
This improves performance in most loops, and is noticable in many
applications.

Change-Id: Ibe42b509b50a13f19758fd923f31d703e33a51c6
Signed-off-by: Henrik Smiding <henrik.smiding@stericsson.com>
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Suppress loop suspend checks.

Suppresses the suspend checks generated by the JIT compiler,
for small loops. This improves performance and code size of loops.

Conflicts:
	vm/compiler/Loop.h

Change-Id: I5df70422668eb53c7789899823586daeee265633
Signed-off-by: Henrik Smiding <henrik.smiding@stericsson.com>
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Allow use of cbz/cbnz for conditional branch gen.

Optimize conditional branch generation when comparing
with zero for ARM JIT. When possible use cbz/cbnz
instead of cmp+beq/cmp+bne.

This improves performance for usecases involving
code execution in Dalvik.

Change-Id: I8f7c44c87eb73d4da00a48fd86220a62cb0515f5
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Combine add with shift.

Optimize logical shift for ARM JIT.
Whenever logical shift is followed by an add,
replace it with an add capable of performing
the shift in the same instruction.

This improves performance for usecases
involving code executing in Dalvik.

Change-Id: I3cb807b6d6ef4b053a19e2703676a93a930eb963
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Use rsb and shift in easy multiply.

For easy multiplication using reverse subtract (when
lit is 2^n-1) use the barrel shifter for rsb.

This improves arithmetic performance for code executing
in Dalvik. E.g String.hashCode.

Change-Id: Ifb086dcec344b30fd3e392ac21d508b43e820cdc
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Combine shift & sub for monitor unlock.

Optimize monitor unlock for ARM Thumb2 JIT.
Monitor unlock performs a logical shift left
and sub, replace it with a sub capable of
performing the shift in the same instruction.

This improves performance for usecases involving code
executing in Dalvik.

Change-Id: Iaf062d750c3bc941926f3c3b8a64dc9c7984a477
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Combine add with shift and offset for array load & store.

Optimize long and double array load / store for ARM JIT.
Array load / store performs a logical shift left and add,
replace it with add capable of performing shift in the
same instruction.
Array load / store performs an add instead of using offset
for vldr/vstr. Replace the add and vldr/vstr with a vldr/vstr
that is capable of handling offset.

This improves performance for usecases involving long and double
array code execution in Dalvik. E.g WindowOrientation.

Conflicts:
	vm/compiler/codegen/arm/Thumb/Gen.cpp
	vm/compiler/codegen/arm/Thumb2/Gen.cpp

Change-Id: I90220c349ab936cdba1987139ccdf4dc31d7bbb0
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Use vmla.f64 instead of vmuld + vaddd.

Optimize Java double floating-point performance for ARM JIT.
Whenever a double mul is followed with a double add,
replace it with a combined mul and add instruction.

This improves double arithmetic performance for code executing
in Dalvik.

Change-Id: Ia4fccf4fa53aa9fb4a76cbf388f5ea16dcef32b7
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
dalvik: revert recent performance patches

*some of these cause crashes in some apps/games

Revert "JIT: Use vmla.f64 instead of vmuld + vaddd."

This reverts commit a3f3da237d7034d525021bd539d634f64f8e0f3a.

Revert "JIT: Combine add with shift and offset for array load & store."

This reverts commit 54895a9d9d2f283b2d98385b2d20c656a3fe59ff.

Revert "JIT: Combine shift & sub for monitor unlock."

This reverts commit 638db2ac4522c434091aa343f085f7eeb9cc914e.

Revert "JIT: Use rsb and shift in easy multiply."

This reverts commit 0a7e8d3986ddb87045d3de6390cbf0ee6735505a.

Revert "JIT: Combine add with shift."

This reverts commit 4ea7a655c64764bba695f4a7e6cd31620d4641f7.

Revert "JIT: Allow use of cbz/cbnz for conditional branch gen."

This reverts commit 4947e2c49c80d686f925d7bb62055426aa7d6278.

Revert "JIT: Suppress loop suspend checks."

This reverts commit d81690b739fb0d8bb331bffc4a6ed27aa2bc0c0a.

Revert "JIT: Hoist loop load operations above loop."

This reverts commit 1eeb7b9fdbfe6b19ca38c33534857ba79b8b9444.

Change-Id: I52d7f69db2a9b23c17b79a68deb5c492bac7dae0