Initial commit including a CORDIC core in MyHDL.
Add PRNG and ignore rules.
Add defaults for parameters and RENAME parameter.

This adds default values for some of the parameters. Also a RENAME
parameter is added, which changes the func_name of the function.

This is a hack to change the VHDL entity name in some cases.
Add NCO core with parameterization UI.
Add buttons to export to VHDL and Verilog.
Add ignore and __init__.py.
Add PDF overview, as the TikZ document is not as useful for others.
Update .gitignore files.
Add copyright headers.