aarch64: Implement lengthening simd add/sub operations.

{U,S}{ADD,SUB}L{,2} -- based on existing UMULL/SMULL operations.
aarch64: Implement simd vector FCMEQ/FCMGE/FCMGT/FCMLE/FCMLT instructions.

Both 3-same and compare-with-zero variants have been added.
aarch64: Remove dead simd scalar NEG code.

Only vector case should be handled in handle_simd_misc.
aarch64: Implement simd vector faddp.
aarch64: Implement several FMIN/FMAX variants

Implement simd vector fminnm/fmaxnm/fminnmp/fmaxnmp and across-vector fmin/
fmax/fminnm/fmaxnm. Also fix second-operand location for the pairwise ops.
aarch64: Implement simd scalar addp.

Only a pair of 64-bit integers are supported for this instruction type.
aarch64: Implement simd vector * indexed element operations.

Only a subset so far - MUL, MLA, MLS, FMUL.
aarch64: Implement simd vector FSQRT.