allow multiple keys for is
merge
Fix width inference bug for UInt(1) << io.x

Bits.maxNum's implementation was dubious, and Node.maxNum seemed
to do the trick.  (That said, Node.maxNum should probably throw
an exception, and Bits.maxNum should be give Node.maxNum's old
implementation.  It doesn't make sense for Node to be an unsigned
integer by default.)
Make ROMs synthesizable; remove O(n^2) code

"initial" => "always @(*)"
String => StringBuilder
Fix Mux(cond, SInt, UInt)

But the Mux implementation is still super ghetto...
Clean up isLit/litOf tomfoolery
fix: update scct to 0.2.1 after 0.2 was removed from maven repo
add option to build with Maven3 - thanks Rupert
Improve Mux1H QoR

The previous implementation did not take advantage of the one-hot
property of the input, resulting in a priority encoder.

I also removed some redundant constructors (leveraging Vec <: Seq).
Improve PriorityEncoderOH QoR

Exposing a higher-level priority encoder structure improves QoR for
Synopsys DC, at least.  (It also results in fewer Chisel nodes.)
Remove old "otherwise" object

This appears to be a holdover from when "when" statement priority was
inverted.  Now it only serves to create bugs.
Fix Vec.fill(0)

Vec.apply previously examined the first element of the input, which didn't
exist for Vec.fill(0).  Also, since ROM and Vec now use clone, they no
longer need to be passed a gen.
fix bug in Cpp.scala when block has zero strings
Handle incorrect bus extraction in the front-end

Things like foo(0,1) (instead of the correct foo(1,0)) result in helpful
error messages, rather than incorrect Verilog.
Fix bug causing invalid verilog for bit indexing
doc updates
Fix VCD compilation errors
fix memWrite inference problem and update flo backend to at least be close to correct on multiword
merge memWrite inference problem and flo backend updates
make clean removes left-overs