arm: tegra: Set bit 22 in PL310 AuxCtlr register, like in S5PV310 and VExpress. See comment for details.

If we clear the bit 22 in the PL310, we'll transform normal shared non-cacheable reads
into cacheable no-allocate reads.
Now, in the Linux kernel, coherent DMA buffers always have a cacheable alias because
of the linear mapping, so, the processor can load cache lines speculatively.

Then, if we clear the bit22, non-cacheable reads would get to those cache lines
and that will lead to buffer corruption.
So, IMHO, it's a sage idea to set it.
Code borrowed from kholk