cpu: Remove incorrect branch predictor drain checks

The branch predictor unit incorrectly checked that the prediction
history was empty when the system is drained. This is an incorrect
assumption since the predictor isn't affected by a drain.
base: Make the Python module loader PEP302 compliant

The custom Python loader didn't comply with PEP302 for two reasons:

 * Previously, we would overwrite old modules on name
   conflicts. PEP302 explicitly states that: "If there is an existing
   module object named 'fullname' in sys.modules, the loader must use
   that existing module".

 * The "__package__" attribute wasn't set. PEP302: "The __package__
   attribute must be set."

This changeset addresses both of these issues.
dev: Clean up MC146818 register (A & B) handling

Rewrite reg A & B handling to use the bitunion stuff instead of bit
masking. Add better error messages when the kernel tries to enable
unsupported stuff.
dev: Add support for disabling ticking and the divider in MC146818

Some Linux versions disable updates (regB.set = 1) to prevent the chip
from updating its internal state while the OS is updating it. Support
for this was already there, this patch merely disables the check in
writeReg that prevented it from being enabled. The patch also includes
support for disabling the divider, which is used to control when clock
updates should start after setting the internal RTC state.

These changes are required to boot most vanilla Linux distributions
that update the RTC settings at boot.
arch: Create a method to finalize physical addresses in the TLB

Some architectures (currently only x86) require some fixing-up of
physical addresses after a normal address translation. This is usually
to remap devices such as the APIC, but could be used for other memory
mapped devices as well. When running the CPU in a using hardware
virtualization, we still need to do these address fix-ups before
inserting the request into the memory system. This patch moves this
patch allows that code to be used by such CPUs without doing full
address translations.
kvm: Use the address finalization code in the TLB

Reuse the address finalization code in the TLB instead of replicating
it when handling MMIO. This patch also adds support for injecting
memory mapped IPR requests into the memory system.
kvm: Fix the memory interface used by KVM

The CpuPort class was removed before the KVM patches were committed,
which means that the KVM interface currently doesn't compile. This
changeset adds the BaseKvmCPU::MemPort class which derives from
MasterPort. This class is used on the data and instruction ports
instead of the old CpuPort.
config: Add missing CPUs to --restore-with-cpu

The --restore-with-cpu option didn't use CpuConfig.cpu_names() to
determine which CPU names are valid, instead it used a static list of
known CPU names. This changeset makes the option parsing code use the
CPU list from the CpuConfig module instead.
kvm: Add support for disabling coalesced MMIO

Add the option useCoalescedMMIO to the BaseKvmCPU. The default
behavior is to disable coalesced MMIO since this hasn't been heavily
tested.
x86: Add helper functions to access rflags

The rflags register is spread across several different registers. Most
of the flags are stored in MISCREG_RFLAGS, but some are stored in
microcode registers. When accessing RFLAGS, we need to reconstruct it
from these registers. This changeset adds two functions,
X86ISA::getRFlags() and X86ISA::setRFlags(), that take care of this
magic.
x86: Fix bug when copying TSC on CPU handover

The TSC value stored in MISCREG_TSC is actually just an offset from
the current CPU cycle to the actual TSC value. Writes with
side-effects to the TSC subtract the current cycle count before
storing the new value, while reads add the current cycle count. When
switching CPUs, the current value is copied without side-effects. This
works as long as the source and the destination CPUs have the same
clock frequencies. The TSC will jump, sometimes backwards, if they
have different clock frequencies. Most OSes assume the TSC to be
monotonic and break when this happens.

This changeset makes sure that the TSC is copied with side-effects to
ensure that the offset is updated to match the new CPU.
cpu: Add support for scheduling multiple inst/load stop events

Currently, the only way to get a CPU to stop after a fixed number of
instructions/loads is to set a property on the CPU that causes a
SimLoopExitEvent to be scheduled when the CPU is constructed. This is
clearly not ideal in cases where the simulation script wants the CPU
to stop at multiple instruction counts (e.g., SimPoint generation).

This changeset adds the methods scheduleInstStop() and
scheduleLoadStop() to the BaseCPU. These methods are exported to
Python and are designed to be used from the simulation script. By
using these methods instead of the old properties, a simulation script
can schedule a stop at any point during simulation or schedule
multiple stops. The number of instructions specified when scheduling a
stop is relative to the current point of execution.
kvm: Dump state before panic in KVM exit handlers
kvm: Update the system's totalNumInsts on exit from KVM

Update the system's totalNumInst counter when exiting from KVM and
maintain internal an absolute instruction count instead of relying on
the one from perf.
arm: Fix compilation error in m5 utility

Changeset 5ca6098b9560 accidentally broke the m5 utility. This
changeset adds the missing co-processor call used to trigger the
pseudo-op in ARM mode and fixes an alignment issue that caused some
pseudo-ops to leave thumb mode.
arm: Add support for the m5fail pseudo-op