Start Opus pcie reference design
Add simple hardware with just a uart and bram
wip
This probably wasn't needed...

But I didn't feel like rebuilding again.
Add software
Got to 8 lanes

Also added the makefile.
Update readme
Go back to 4 lanes to help with timing
Use our own bitfile for initialization
Add Driver source

For some reason, on my test machine, I can load the driver once and it
will work. When I load the driver a second time, reads fail, but I can
still write.
Update readme with fedora 19
Merge branch 'master' of https://github.com/rphoover/opus-pcie-ref