TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should look
at all of the operands. Previously it was skipping over implicit operands which
cause infinite looping when the two-address pass try to reschedule a
two-address instruction below the kill of tied operand.

I'm unable to come up with a reasonably sized test case.
rdar://13747577


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180906 91177308-0d34-0410-b5e6-96231b3b80d8
Add a test for the foldSelectICmpAndOr fix committed in r180779.

This tests a case where C1 and C2 were the same but X and Y were different
widths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180907 91177308-0d34-0410-b5e6-96231b3b80d8
Rewrite X86 codegen regression test with FileCheck



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180910 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid duplicating logic on frame register selecting when lowering frameaddr

No functionality change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180912 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid duplicating logic on frame register selecting when lowering eh_return

No functionality change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
80-col fixup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915 91177308-0d34-0410-b5e6-96231b3b80d8
Added table of contents declaration in CommandLine Library documentation.

Contributed-by:  Dan Liew <daniel.liew@imperial.ac.uk>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180919 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: remove nonsense select pattern

Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Use new tablegen syntax for patterns

All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Honor __builtin_expect by using branch probabilities.

  * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
  Given a jump opcode return the right pred.new jump opcode with
  a taken vs not-taken hint based on branch probabilities provided
  by the target independent module.
  * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
  * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
  Enhance existing function use branch probabilities like
  HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
Provide an API to temporarily suppress DebugLocations from being attached
to emitted instructions.  Use this if you want an instruction to be
counted towards the prologue or if there is no useful source location.

rdar://problem/13442648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180929 91177308-0d34-0410-b5e6-96231b3b80d8
TBAA: remove !tbaa from testing cases if not used.

This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180935 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix the head Mips16RegisterInfo.cpp comment

...aka a test commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon - Add peephole optimizations for zero extends.

	* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
Replaced usages of size_type with size_t to be more consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180947 91177308-0d34-0410-b5e6-96231b3b80d8
We don't want FP elimination when doing an Apple-style build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180949 91177308-0d34-0410-b5e6-96231b3b80d8
[GV] Remove dead code which is really difficult to decipher.

Actually it took me couple of hours trying to make sense of them and
only to find they are dead code.  I guess the original author used
"allSingleSucc" to indicate if there are any critial edge emanating
from some blocks, and tried to perform code motion (actually speculation)
in the presence of these critical edges; but later on he/she changed mind
and decided to perform edge-splitting first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180951 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Prettier asmPrint of Alu

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Improve asmPrint of ALU clause

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8