Minor update to cube_driver.c comments
Fixed row/column order in FPGA. Reorganized Software directory.
Reorganized directories
Server WIP
Reorganized source directories
Updated Makefiles and directory structure
Updated server and client code
Server software working
Server software working
Reorganized python_client directory
Reorganized python_client directory
Fixed major issue with ports 0 & 1 not working when 4 panels are connected. Solution: widen the SCLK pulses to the TLC chips. Timing was out of spec before.
Updated python_client
Updated server code