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top: add flash external clock sources
eb-flash: bug fix for sector size auto-detect causing premature erase
fix pexarria5 RX timings and update project files

Manual assignment of not only PLLs, but also PLL counters and
clock networks seems necessary to ensure a good WR synthesis.
track subprojects and use GSI config for wrpc-sw
pexarria5: register usb io pins
pexarria5: logic lock flash IO registers
exploder: fix pps output
scu: fix pps output
wr-cores: include butis alignment fix
pexarria5: use FEBEX-AD6 breakout board

There are problems with the reference fPLL.
These LVDS outputs make it possible to debug.
scu+exploder: PLL settings were to wrong name
pexarria5: fix fPLL reset bug => working white rabbit
flash: force 10 dummy cycles for 100MHz operation
flash: disable reconfig on older devices
spi flash: fix some hidden off-by-one bugs
eb-flash: robustify wait loop and detect old flash chips
initial commit of wb_mil_scu
exploder: remove obsolete cof file
add mil pll