arm: Kconfig: Disable CONFIG_OABI_COMPAT feature on SMP targets

When this option is enabled to support Old ABI, it introduces
a race condition in swap-out code on SMP, such that
instruction is available to the instruction stream (SWI
instruction) but not the data stream.

CPU0		CPU1
clears pte
		executes instruction from page,
		already has I-TLB but no D-TLB entry,
		takes SWI exception
		tries to load instruction, data abort
tlb flush

Therefore, disable this feature on SMP targets.

Change-Id: I4cc4e6924cfcffad391fe2e68d5aa62eee613b0e
Signed-off-by: Jay Chokshi <jchokshi@codeaurora.org>
ARM: hw_breakpoint: Clear breakpoints before enabling monitor mode

The reset value of the BCR, BVR, WCR, and WVR registers are all
UNKNOWN on ARMv7. Unfortunately, reset_ctrl_regs() clears these
registers *after* enabling monitor mode, not before, and so some
implementations may experience UNPREDICTABLE behavior if the
reset values of these registers are non-zero. Clear the
breakpoints before enabling monitor mode so that we don't
experience boot hangs/loops due to breakpoints being enabled
out of reset.

Change-Id: I029fbe40725e803183544ddd6fe40285de4137e8
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
ARM: hw_breakpoint: enable HAVE_HW_BREAKPOINT feature flag

HAVE_HW_BREAKPOINT was disabled temporarily from commit
480a82f59712136b51ee5ca05c4f22c1738010c5. Issue not seen with the
latest kernel hence re-enable the feature and fix merge issue from
previous kernel upgrade.

Change-Id: Ia6e7e8282c848dd73108e4d951b3375bb7caa63c
Signed-off-by: Jin Hong <jinh@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
msm: pm-8x60: Disable premption in msm_pm_enable_retention

msm_pm_retention_enable() makes smp_call_function_many to ensure that
when a retention is disabled, the cores come out of its low power mode.
Per the smp_call_function_many documentations, preemption should be
disabled before invoking the API.

CRs-fixed: 463188
Change-Id: I4ae9137e8f8e821af729becd0e2d6e6886d5e787
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
ARM: proc: Add Krait proc info

Add processor info for the Qualcomm, Inc. Krait family of
processors, to use the generic ARMv7 initialisation
procedure but explicitly enable the IDIV hardware
capability flag.

Change-Id: I080f60189fada2e4f87c79c6b8ef522cdc070759
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Revert "msm: cpufreq: Remove cross-calling limitation"

This reverts commit be01a17afb6b6e85456217caa1ac11eb0b6674e1.

Re-introduce cross calling in cpufreq to prevent race conditions in the
hardware when changing PLLs.

A core could be in retention, while another core, could try and set the
frequency of the core in retention, causing a change in PLL and when the
core exits retention, the PLL mismatch could hang the SPM state machine.

Change-Id: I99b454a0f146652f2d8a369f79f6d35748160dcb
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
M2: (FIXUP): msm: pm: Update spm retention sequence to support per core retention

On krait revision < 3, power driver is not using full spm sequence and
calling into trustzone as a part of executing krait retention.
Also krait retention is not supported on secondary cores.

krait pass3 is upgraded to use full spm sequence, hence add support
for per core retention and avoid calling into trustzone
while executing retention.

*detule: sync to 8960 board file.  Previous version of this patch that I
brought from msm-3.4 didn't have the full spm register update.  The
jb_2.5 version of the patch did.

CRs-fixed: 437281
Change-Id: I6a2b3d7c4d0fd5b9a340957b16b940b7a09bbd91
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Merge remote-tracking branch 'upstream/cm-10.1' into HEAD