Added ground-stitch vias near USB SS RX and TX pair vias, as per Cypress application note.
Adjusted USB 3.0 shield zone to reduce potential for coupling with differential pairs.
Changed some zones to have more 45-degree angles.
Rerouted DDR2 VREF to not break up V1P8 power plane. Removed prior via stitching.
More miscellaneous power plane cleanup, mostly to reduce coupling between unrelated planes and signals.