[ARM] generic_timer: Fix CNTHCTL access in generic_timer_clockchip_init()

Each host core has its own copy of Generic Timer registers, including
"CNTHCTL", so we need to configure CNTHCTL{PL1PCEN, PL1PCTEN} to "1"
on each host core.

The current implementation works because the "reset" value of
CNTHCTL{PL1PCEN, PL1PCTEN} are both 1. For correctness and easier
understanding of the code, we should set CNTHCTL{PL1PCEN, PL1PCTEN}
on each host core.

This patch fixes CNTHCTL programming in generic_timer_clockchip_init()
and also adds code to freeup resources if generic_timer_clockchip_init()
failed.

Reported-by: Po-wen Cheng <sting.cheng@gmail.com>
Signed-off-by: Anup Patel <anup@brainfault.org>