Update Assembler to point to current Octavo file path
Fixed port names.
Debugging: generate blocks required and fixed localparams and port names
Conditional instantiation of middle if < 3 stages
Fixed corner case: don't do anything SIMD if no SIMD lanes specified. Just a generate block 'if'.
Put back old test harness register generator code. Broken.

Needs nesting in a generate loop to work properly, since scalar and
SIMD ports are no longer entirely consecutive across entire DUT periphery.