target-arm: A64: support for ld/st/cl exclusive

This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive load remember the address
and loaded value. The exclusive store throws and an exception which uses
those values to check for equality in a proper exclusive region.

AArch64 also implements new aquire/release loads/stores without the
exclusive part, which merely imposes an ordering on memory operations.
As we run on just one CPU, that's not necessary, but could be done
e.g. by a simple heavy barrier insn.

It's fairly easy to come up with test cases were we don't behave like
hardware - we don't for example model cache line behaviour. However in
the common patterns this works.

For simplicity the exclusive_* fields used have been expanded to 64bits
and 33 bit code will just use half of the field.

from Alexander Graf <agraf@suse.de> aarch64 series 12/60
 and Michael Matz <matz@suse.de> aarch64-1.6 branch
 and Peter Maydell <peter.maydell@linaro.org> aarch64 clean-up

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb):
   - use new gpr_ld API

v4 -> v5 (ajb):
   - merge in later fixes from Matz
   - fix bug with using ZR for status
   - add sp alignment check
   - fixup bogus whitespace

v5 -> v6 (ajb):
   - better naming of goto fields
   - implement clrex
   - clear exclusive lock after strex
   - clear exclusive lock after exceptions
   - fix up checkpatch violations
rm unused field
default-configs: Add config for aarch64-linux-user

Add a config for aarch64-linux-user, thereby enabling it as
a valid target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>